公开(公告)号：US20180101475A1

公开(公告)日：2018-04-12

申请号：US15839665

申请日：2017-12-12

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Lei FANG ,  Xiongli GU ,  Weiguang CAI

IPC: G06F12/0817 ,  G06F12/0808 ,  G06F12/084

CPC classification number: G06F12/0817 ,  G06F12/0808 ,  G06F12/082 ,  G06F12/084 ,  G06F12/121 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/62

Abstract: Embodiments of the present disclosure disclose a method for combining entries, including: determining N to-be-combined entries, where a cache block indicated by an entry label of each entry of the N entries belongs to a combination range, and the combination range indicates 2a cache blocks; and combining the N entries into a first entry, where an entry label of the first entry indicates the 2a cache blocks, and a sharer number of the first entry includes a sharer number of each entry of the N entries. According to the method, entries in a directory can be combined effectively, thereby improving directory usage efficiency.

公开(公告)号：US20190026225A1

公开(公告)日：2019-01-24

申请号：US16138824

申请日：2018-09-21

Applicant: Huawei Technologies Co., Ltd.

Inventor： Xiongli GU ,  Lei FANG ,  Peng LIU ,  Qi HU

IPC: G06F12/0817

Abstract: A multiple chip multiprocessor cache coherence operation method and a multiple chip multiprocessor are disclosed. The method includes: receiving a write request for a first data block; finding, in an on-chip directory of the first processor chip, an on-chip directory entry corresponding to the first data block based on an identifier of the first data block, determining, from the found on-chip directory entry, a core identifier of a processor core storing the first data block, sending, to the processor core corresponding to the core identifier, an instruction message for deleting the first data block, skipping sending an inter-chip directory query request for the first data block, and instructing the first processor core to write the to-be-written data into a private cache of the first processor core.

公开(公告)号：US20170364442A1

公开(公告)日：2017-12-21

申请号：US15675929

申请日：2017-08-14

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Xiongli GU ,  Lei FANG ,  Weiguang CAI ,  Peng LIU

IPC: G06F12/0817 ,  G06F12/0846 ,  G06F12/084 ,  G06F12/0864 ,  G06F12/0811

CPC classification number: G06F12/0822 ,  G06F12/08 ,  G06F12/0811 ,  G06F12/0817 ,  G06F12/0828 ,  G06F12/084 ,  G06F12/0846 ,  G06F12/0864 ,  G06F2212/1044 ,  G06F2212/283 ,  G06F2212/314 ,  G06F2212/6032 ,  G06F2212/621

Abstract: The present disclosure discloses a method for accessing a data visitor directory in a multi-core system, a directory cache device, a multi-core system, and a directory storage unit. The method includes: receiving a first access request sent by a first processor core, where the first access request is used to access an entry, corresponding to a first data block, in a directory; determining, according to the first access request, that a single-pointer entry array has a first single-pointer entry corresponding to the first data block; when determining, according to the first single-pointer entry, that a sharing entry array has a first sharing entry associated with the first single-pointer entry, determining multiple visitors of the first data block according to the first sharing entry. According to embodiments of the present disclosure, storage resources occupied by a directory can be reduced.

公开(公告)号：US20190108134A1

公开(公告)日：2019-04-11

申请号：US16211225

申请日：2018-12-05

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Weiguang CAI ,  Xiongli GU ,  Lei FANG

IPC: G06F12/1027

Abstract: A method for accessing an entry in a translation lookaside buffer and a processing chip are provided. In the method, the entry includes at least one combination entry, and the combination entry includes a virtual huge page number, a bit vector field, and a physical huge page number. The physical huge page number is an identifier of N consecutive physical pages corresponding to the N consecutive virtual pages. One entry is used to represent a plurality of virtual-to-physical page mappings, so that when a page table length is fixed, a quantity of entries in the TLB can be increased exponentially, thereby increasing a TLB hit probability, and reducing TLB misses. In this way, a delay in program processing can be reduced, and processing efficiency of the processing chip can be improved.

公开(公告)号：US20190073315A1

公开(公告)日：2019-03-07

申请号：US16178676

申请日：2018-11-02

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Lei FANG ,  Weiguang CAI ,  Xiongli GU

IPC: G06F12/1027 ,  G06F12/1009 ,  G06F12/0842

CPC classification number: G06F12/1027 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0842 ,  G06F12/1009 ,  G06F12/128 ,  G06F2212/684

Abstract: A translation lookaside buffer (TLB) management method and a multi-core processor are provided. the method includes: receiving, by a first core, a first address translation request; querying a TLB of the first core based on the first address translation request; determining that a first target TLB entry corresponding to the first address translation request is missing in the TLB of the first core, obtaining the first target TLB entry; determining that entry storage in the TLB of the first core is full; determining a second core from cores in an idle state in the multi-core processor; replacing a first entry in the TLB of the first core with the first target TLB entry; storing the first entry in a TLB of the second core. Thereby reducing a TLB miss rate and accelerating program execution.