公开(公告)号：US3675200A

公开(公告)日：1972-07-04

申请号：US3675200D

申请日：1970-11-23

Applicant: IBM

Inventor： BOSSEN DOUGLAS C ,  HENLE ROBERT A ,  HSIAO MU Y ,  MALEY GERALD A ,  PRICER W DAVID

IPC: G06F11/10 ,  G11C29/00 ,  G06F11/08 ,  G06K5/00

CPC classification number: G06F11/1008 ,  G06F11/1076 ,  G11C29/003

Abstract: Errors in parallel binary data produced by a plurality of data track, e.g., a plurality of parallel shift registers, are corrected by a system in which the shift registers which are stuck, i.e., inalterable, are determined and counted. By single Hamming error detection means, the presence of a Hamming error and an indication of the bit position of a single Hamming error is made. Comparison means determine if the indicated Hamming error is coincident with a stuck track. Then, dependent on the parity condition of the data as well as the count of stuck tracks, apparatus is provided for complementing one or more of the stuck tracks and/or correcting the indicated Hamming error.

Abstract translation: 由多个数据磁道（例如多个并行移位寄存器）产生的并行二进制数据的错误由其中确定并计数被卡住的，即不可更改的移位寄存器的系统来校正。 通过单个汉明误差检测装置，进行汉明误差的存在和单个汉明误差的比特位置的指示。 比较装置确定所指示的汉明误差是否与卡盘轨迹一致。 然后，依赖于数据的奇偶校验条件以及卡盘轨迹的计数，提供装置用于补充一个或多个卡住轨迹和/或校正所指示的汉明误差。

公开(公告)号：US3573758A

公开(公告)日：1971-04-06

申请号：US3573758D

申请日：1969-02-27

Applicant: IBM

Inventor： HENLE ROBERT A ,  PRICER W DAVID

IPC: G11C11/411 ,  H03K3/288 ,  G11C11/40 ,  H03K3/286

CPC classification number: H03K3/288 ,  G11C11/4113 ,  G11C11/4116

Abstract: Each of the pair of transistors of a flip-flop storage cell has its collector connected through a nonlinear impedance means to a low constant current source when the cell is in an inactive condition. The nonlinear impedance means for the conducting transistor maintains the ratio of the load impedance means to the base-emitter impedance of the conducting transistor greater than one to maintain the transistors of the cell in the desired bistable state when the transistors are connected to the low constant current source through the nonlinear impedance means.

公开(公告)号：US3697962A

公开(公告)日：1972-10-10

申请号：US3697962D

申请日：1970-11-27

Applicant: IBM

Inventor： BEAUSOLEIL WILLIAM F ,  HO IRVING T ,  JEN TEH-SEN ,  PRICER W DAVID

IPC: G11C11/403 ,  G11C11/406 ,  G11C11/4067 ,  G11C11/4094 ,  H01L23/535 ,  H01L27/07 ,  H01L27/102 ,  G11C11/40

CPC classification number: H01L27/1023 ,  G11C11/403 ,  G11C11/406 ,  G11C11/4067 ,  G11C11/4094 ,  H01L23/535 ,  H01L27/075 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: This specification discloses a stored charged storage cell for implementation in monolithic memories. The storage cells are fabricated in an array form and are connected to accessing means for reading and writing information into and out of the array. An integrated circuit diffused common sensing line is connected to either selected rows or columns for reading and writing. These sensing lines are connected to a switchable current source. The cell itself clamps the output voltage swing and thus reduces power dissipation. The storage cells each comprise a pair of semiconductor elements for storing digital information on an associated parasitic capacitor. The pair of semiconductor devices are interconnected and operated in an AC mode so as to eliminate direct current paths and thus further prevent unnecessary power dissipation.

Abstract translation: 本说明书公开了一种用于在单片存储器中实现的存储的充电存储单元。 存储单元以阵列形式制造并连接到用于将信息读入和写入阵列的访问装置。 集成电路漫射的公共感测线路连接到所选择的行或列用于读取和写入。 这些感测线路连接到可切换的电流源。 电池本身夹紧输出电压摆幅，从而降低功耗。 存储单元各自包括一对半导体元件，用于在关联的寄生电容器上存储数字信息。 该对半导体器件以AC模式互连和操作，以消除直流电流路径，从而进一步防止不必要的功率耗散。