公开(公告)号：US20180240699A1

公开(公告)日：2018-08-23

申请号：US15903909

申请日：2018-02-23

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Ming Mao ,  Peter De Schepper ,  Michael Kocsis

IPC: H01L21/768 ,  H01L21/762 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/033 ,  H01L21/027 ,  H01L23/522 ,  H01L29/06

CPC classification number: H01L21/76802 ,  H01L21/0274 ,  H01L21/033 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31051 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/5226 ,  H01L29/0649

Abstract: An example embodiment may include a method for blocking one or more portions of one or more trenches during manufacture of a semiconductor structure. The method may include (i) providing a substrate comprising one or more trenches, and a dielectric material under the one or more trenches, (ii) providing a first overlayer on the substrate, thereby filling the one or more trenches, the first overlayer having a planar top surface, a top portion of the first overlayer, comprising the top surface, being etchable selectively with respect to a condensed photo-condensable metal oxide, (iii) covering a first area of the top surface, situated directly above the one or more portions and corresponding thereto, with a block pattern of the condensed photo-condensable metal oxide, thereby leaving a second area of the top surface, having at least another portion of at least one of the trenches thereunder, uncovered.