公开(公告)号：US10582143B2

公开(公告)日：2020-03-03

申请号：US15990124

申请日：2018-05-25

Applicant: IMEC VZW

Inventor： Roeland Vandebriel ,  David San Segundo Bello

IPC: H04N5/378 ,  H04N5/376 ,  H04N5/353 ,  H04N5/347 ,  G05B19/045 ,  H04N5/3745 ,  H04N5/345 ,  G06F8/656 ,  H04N5/341

Abstract: An image sensor comprises: an array (102) of pixels (104) arranged in rows and columns; readout circuitry (110) for reading out image information from pixels (104) in the array (102) of pixels (104); signal lines (112) for providing control signals to the pixels (104) in the array (102) and/or the readout circuitry (110); a programmable sequence controller (114) configured to control the control signals provided on the signal lines (112), said programmable sequence controller (114) comprising: at least one programmable signal controlling state machine (140), which is configured to define a sequence of states and to define control parameters for the states in the sequence, wherein the control parameters include the control signals to be provided on at least one signal line (112) for controlling at least one of a row of pixels (104) or the readout circuitry (110).

公开(公告)号：US20190165791A1

公开(公告)日：2019-05-30

申请号：US16203402

申请日：2018-11-28

Applicant: IMEC vzw

Inventor： Roeland Vandebriel ,  Geert Van der Plas ,  Vladimir Cherman

IPC: H03K21/02 ,  G11C5/04 ,  G11C7/20 ,  H01L25/065 ,  H03K5/153

CPC classification number: H03K21/023 ,  G11C5/025 ,  G11C5/04 ,  G11C7/20 ,  G11C8/12 ,  H01L23/481 ,  H01L23/522 ,  H01L23/544 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L2223/5444 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H03K5/153 ,  H03K21/026

Abstract: An assembly including a carrier substrate and at least one group of interconnected integrated circuit modules mounted thereon is disclosed. The modules are provided with a connection for transmitting a clock signal through the group of interconnected modules. The modules are also provided with digital input ports and output ports and a logic circuit configured for identifying the position of the modules in the group on the basis of a count of the clock pulses, and on the basis of the logic state of the input and output ports. In one aspect, a method involves the transfer of a token in the form of one or more logic states, through the group of modules, from a first module to a last module, resulting in the identification of all modules in a progressive manner.

公开(公告)号：US10382042B2

公开(公告)日：2019-08-13

申请号：US16203402

申请日：2018-11-28

Applicant: IMEC vzw

Inventor： Roeland Vandebriel ,  Geert Van der Plas ,  Vladimir Cherman

IPC: H03K21/02 ,  G11C5/04 ,  G11C7/20 ,  H03K5/153 ,  H01L25/065

Abstract: An assembly including a carrier substrate and at least one group of interconnected integrated circuit modules mounted thereon is disclosed. The modules are provided with a connection for transmitting a clock signal through the group of interconnected modules. The modules are also provided with digital input ports and output ports and a logic circuit configured for identifying the position of the modules in the group on the basis of a count of the clock pulses, and on the basis of the logic state of the input and output ports. In one aspect, a method involves the transfer of a token in the form of one or more logic states, through the group of modules, from a first module to a last module, resulting in the identification of all modules in a progressive manner.