公开(公告)号：US20220214972A1

公开(公告)日：2022-07-07

申请号：US17565594

申请日：2021-12-30

Applicant: IMEC VZW

Inventor： Manu Komalan Perumkunnil ,  Geert Van der Plas

IPC: G06F12/0815 ,  G06F12/1027 ,  G06F12/0875

Abstract: Example embodiments relate to integrated circuits with 3D partitioning. One embodiment includes an integrated circuit. The integrated circuit includes a first integrated circuit layer that includes processing cores. The integrated circuit also includes a second integrated circuit layer that includes memory arrays associated with processing cores. Additionally, the integrated circuit includes an intermediate integrated circuit layer interconnected with the first and second integrated circuit layers and including memory control logic and interface circuitries for managing data exchange between the processing cores and the memory arrays.

公开(公告)号：US20170062431A1

公开(公告)日：2017-03-02

申请号：US15245671

申请日：2016-08-24

Applicant: IMEC VZW

Inventor： Geert Hellings ,  Geert Van der Plas ,  Mirko Scholz

IPC: H01L27/092 ,  H01L21/266 ,  H01L27/06 ,  H01L21/033 ,  H01L29/808 ,  H01L29/66

CPC classification number: H01L27/0928 ,  H01L21/0332 ,  H01L21/265 ,  H01L21/266 ,  H01L21/761 ,  H01L27/0629 ,  H01L27/098 ,  H01L29/1058 ,  H01L29/456 ,  H01L29/66128 ,  H01L29/66893 ,  H01L29/66901 ,  H01L29/808 ,  H01L29/8611

Abstract: The disclosed technology relates to semiconductors, and more particularly to a junction field effect transistor (JFET). In one aspect, a method of fabricating a JFET includes forming a well of a first dopant type in a substrate, wherein the well is isolated from the substrate by an isolation region of a second dopant type. The method additionally includes implanting a dopant of the second dopant type at a surface of the well to form a source, a drain and a channel of the JFET, and implanting a dopant of the first dopant type at the surface of the well to form a gate of the JFET. The method additionally includes, prior to implanting the dopant of the first type and the dopant of the second type, forming a pre-metal dielectric (PMD) layer on the well and forming contact openings in the PMD layer above the source, the drain and the gate. The PMD layer has a thickness such that the channel is formed by implanting the dopant of the first type and the dopant of the second type through the PMD layer. The method further includes, after implanting the dopant of the first type and the dopant of the second type, siliciding the source, the drain and the gate, and forming metal contacts in the contact openings.

Abstract translation: 所公开的技术涉及半导体，更具体地涉及结型场效应晶体管（JFET）。 一方面，一种制造JFET的方法包括在衬底中形成第一掺杂剂阱，其中阱通过第二掺杂剂类型的隔离区与衬底隔离。 该方法另外包括在阱的表面处注入第二掺杂剂类型的掺杂剂以形成JFET的源极，漏极和沟道，以及在阱的表面处注入第一掺杂剂类型的掺杂剂，以形成 JFET栅极。 该方法还包括在植入第一类型的掺杂剂和第二类型的掺杂剂之前，在阱上形成预金属电介质（PMD）层并在源上形成PMD层中的接触开口，漏极和 大门。 PMD层的厚度使得通过PMD层注入第一类掺杂剂和第二类掺杂剂形成沟道。 该方法还包括在注入第一类型的掺杂剂和第二类型的掺杂剂之后，将源极，漏极和栅极硅化，并在接触开口中形成金属接触。

公开(公告)号：US20240213120A1

公开(公告)日：2024-06-27

申请号：US18393221

申请日：2023-12-21

Applicant: IMEC vzw

Inventor： Herman Oprins ,  Geert Van der Plas ,  Eric Beyne ,  Pieter Woeltgens

IPC: H01L23/48 ,  H01L23/46 ,  H01L23/528 ,  H01L25/065

CPC classification number: H01L23/481 ,  H01L23/46 ,  H01L23/5283 ,  H01L25/0657

Abstract: A micro-electronic component, for example an integrated circuit chip, is provided. In one aspect, the component includes a front-end-of-line (FEOL) portion and a back-end-of-line (BEOL) portion at its front side. A back side power delivery network (PDN) is present at the back side of the component, with via connections connecting the PDN to the FEOL and BEOL portions. The back side PDN includes a “dry part” and a “wet part,” where the dry part includes multiple interconnect levels of the PDN embedded in a dielectric material. The “wet part” includes the remaining PDN levels which are not embedded in a dielectric but which are part of a manifold structure configured to receive therein a flow of cooling fluid in order to remove heat generated by the devices in the FEOL portion.

公开(公告)号：US10825806B2

公开(公告)日：2020-11-03

申请号：US16215492

申请日：2018-12-10

Applicant: IMEC vzw

Inventor： Gaspard Hiblot ,  Geert Van der Plas ,  Stefaan Van Huylenbroeck

IPC: H01L27/02 ,  H01L21/3065 ,  H01L21/768 ,  H01L23/48 ,  H01L23/60

Abstract: The disclosed technology relates to a semiconductor integrated circuit that comprises a semiconductor device which has a port to be protected from Plasma-Induced Damage due to electric charge that may accumulate at the port during a plasma-processing step, and a protection circuit that is provided to the integrated circuit. In one aspect, the protection circuit comprises a discharge path, a control terminal, and a plasma pick-up antenna connected to the control terminal. The protection circuit further comprises a bipolar transistor which has a base connected to the control terminal. Such protection circuit is much more efficient in allowing charge transfer from the device port to a reference voltage terminal.

公开(公告)号：US20190165791A1

公开(公告)日：2019-05-30

申请号：US16203402

申请日：2018-11-28

Applicant: IMEC vzw

Inventor： Roeland Vandebriel ,  Geert Van der Plas ,  Vladimir Cherman

IPC: H03K21/02 ,  G11C5/04 ,  G11C7/20 ,  H01L25/065 ,  H03K5/153

CPC classification number: H03K21/023 ,  G11C5/025 ,  G11C5/04 ,  G11C7/20 ,  G11C8/12 ,  H01L23/481 ,  H01L23/522 ,  H01L23/544 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L2223/5444 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H03K5/153 ,  H03K21/026

Abstract: An assembly including a carrier substrate and at least one group of interconnected integrated circuit modules mounted thereon is disclosed. The modules are provided with a connection for transmitting a clock signal through the group of interconnected modules. The modules are also provided with digital input ports and output ports and a logic circuit configured for identifying the position of the modules in the group on the basis of a count of the clock pulses, and on the basis of the logic state of the input and output ports. In one aspect, a method involves the transfer of a token in the form of one or more logic states, through the group of modules, from a first module to a last module, resulting in the identification of all modules in a progressive manner.

公开(公告)号：US20190074231A1

公开(公告)日：2019-03-07

申请号：US16121369

申请日：2018-09-04

Applicant: IMEC VZW

Inventor： Gaspard Hiblot ,  Geert Van der Plas ,  Stefaan Van Huylenbroeck

IPC: H01L21/66 ,  H01L21/265 ,  G01L1/18

Abstract: An example embodiment may include a sensor for monitoring and/or measuring stress in a semiconductor component. The component may include a substrate formed of a semiconductor material. The substrate may include a planar main surface. The sensor may include at least one slanted surface of the substrate material, the slanted surface being defined by an oblique inclination angle with respect to the main surface of the substrate. The sensor may also include at least one straight resistive path extending on at least part of the slanted surface and a plurality of contacts and terminals for accessing the at least one resistive path. The contacts and terminals may allow for the measurement of an electrical resistance of the resistive path and an assessment of a shear stress in a plane that is not parallel to the main surface of the substrate.

公开(公告)号：US10811315B2

公开(公告)日：2020-10-20

申请号：US16456833

申请日：2019-06-28

Applicant: IMEC vzw

Inventor： Gaspard Hiblot ,  Stefaan Van Huylenbroeck ,  Geert Van der Plas

IPC: H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L25/065 ,  H01L23/538 ,  H01L23/48 ,  H01L23/00

Abstract: A method of producing a through semiconductor via (TSV) connection is disclosed. In one aspect, an opening of the TSV is produced for contacting a first semiconductor die bonded to a second die or to a temporary carrier. The first die includes fin-shaped devices in the front end of line of the die. Etching of the TSV opening does not end on a metal pad, but the opening is etched until reaching a well that is formed of material of a first doping type and formed in the first die amid semiconductor material of a second doping type opposite the first. After filling the TSV opening with a conductive material, the TSV connects to a conductor of an intermediate metallization (IM) of the first die through at least one fin extending from the well and connected to the conductor. A package of dies comprising at least one TSV produced by the above method is also disclosed.

公开(公告)号：US09847336B2

公开(公告)日：2017-12-19

申请号：US15245671

申请日：2016-08-24

Applicant: IMEC VZW

Inventor： Geert Hellings ,  Geert Van der Plas ,  Mirko Scholz

IPC: H01L27/092 ,  H01L21/266 ,  H01L27/06 ,  H01L21/033 ,  H01L29/808 ,  H01L29/66 ,  H01L21/265 ,  H01L21/761 ,  H01L29/10 ,  H01L29/45 ,  H01L29/861

CPC classification number: H01L27/0928 ,  H01L21/0332 ,  H01L21/265 ,  H01L21/266 ,  H01L21/761 ,  H01L27/0629 ,  H01L27/098 ,  H01L29/1058 ,  H01L29/456 ,  H01L29/66128 ,  H01L29/66893 ,  H01L29/66901 ,  H01L29/808 ,  H01L29/8611

Abstract: The disclosed technology relates to semiconductors, and more particularly to a junction field effect transistor (JFET). In one aspect, a method of fabricating a JFET includes forming a well of a first dopant type in a substrate, wherein the well is isolated from the substrate by an isolation region of a second dopant type. The method additionally includes implanting a dopant of the second dopant type at a surface of the well to form a source, a drain and a channel of the JFET, and implanting a dopant of the first dopant type at the surface of the well to form a gate of the JFET. The method additionally includes, prior to implanting the dopant of the first type and the dopant of the second type, forming a pre-metal dielectric (PMD) layer on the well and forming contact openings in the PMD layer above the source, the drain and the gate. The PMD layer has a thickness such that the channel is formed by implanting the dopant of the first type and the dopant of the second type through the PMD layer. The method further includes, after implanting the dopant of the first type and the dopant of the second type, siliciding the source, the drain and the gate, and forming metal contacts in the contact openings.

公开(公告)号：US11621295B2

公开(公告)日：2023-04-04

申请号：US17092130

申请日：2020-11-06

Applicant: IMEC vzw

Inventor： Gaspard Hiblot ,  Shamin Houshmand Sharifi ,  Geert Van der Plas

IPC: H01L27/22 ,  G11C5/06 ,  G11C11/16 ,  H01L43/02 ,  H01L43/12

Abstract: The disclosed technology relates to the field of memory devices including memory arrays, and more particularly, to magnetic memory devices. In one aspect, the disclosed technology provides a method of fabricating a memory device, and the memory device. The method comprises: processing a plurality of selector devices in a semiconductor layer of a first substrate, processing an interconnect layer on a front-side of the semiconductor layer, the interconnect layer comprising an interconnect structure electrically connected to the plurality of selector devices, processing a plurality of memory elements in an oxide layer of the first substrate arranged on a back-side of the semiconductor layer, each memory element being electrically connected to one of the selector devices, and processing one or more vias through the semiconductor layer to electrically connect the memory elements to the interconnect structure.

公开(公告)号：US20230025767A1

公开(公告)日：2023-01-26

申请号：US17869289

申请日：2022-07-20

Applicant: IMEC VZW

Inventor： Gaspard Hiblot ,  Geert Hellings ,  Geert Van der Plas

IPC: H01L23/528 ,  H01L29/66 ,  H01L29/786

Abstract: An example includes a semiconductor structure including a semiconductor layer, front-side logic devices arranged in a front-side of the semiconductor layer, four epitaxial layers on a back-side of the semiconductor layer, where the four epitaxial layers include a first epitaxial layer of a first conductivity type, a second epitaxial layer of a second conductivity type, a third epitaxial layer of the second conductivity type, and a fourth epitaxial layer of the first conductivity type, a plurality of back-side contacts exposed at a back-side surface of the fourth epitaxial layer, where the plurality of back-side contacts include a set of first terminal contacts extending into and contacting the fourth epitaxial layer, a set of second terminal contacts extending into and contacting the second epitaxial layer, a set of first gate contacts extending into the third epitaxial layer, and a set of second gate contacts extending into the first epitaxial layer.