公开(公告)号：US10309925B2

公开(公告)日：2019-06-04

申请号：US15143262

申请日：2016-04-29

Applicant: IMEC VZW

Inventor： Nadine Collaert ,  Voon Yew Thean

IPC: G01N27/414 ,  H01L21/265 ,  H01L29/423 ,  H01L29/66

Abstract: The disclosed technology relates generally to semiconductor devices, and more particularly to semiconductor devices such as field-effect transistor devices configured for biomolecule sensing. In one aspect, a semiconductor chip comprises at least one field-effect transistor device which comprises a source, a drain, a gate stack and a channel region formed between the source and the drain. The gate stack only partially overlaps the channel region at the source side and/or at the drain side, such that a non-overlapped channel region at the source side and/or at the drain side is formed, where the non-overlapped channel region is configured for sensing biomolecules.

公开(公告)号：US20160320336A1

公开(公告)日：2016-11-03

申请号：US15143262

申请日：2016-04-29

Applicant: IMEC VZW

Inventor： Nadine COLLAERT ,  Voon Yew Thean

IPC: G01N27/414 ,  H01L29/423 ,  H01L29/66 ,  H01L21/265

CPC classification number: G01N27/4145 ,  G01N27/414 ,  H01L21/26586 ,  H01L29/42356 ,  H01L29/6653

Abstract: The disclosed technology relates generally to semiconductor devices, and more particularly to semiconductor devices such as field-effect transistor devices configured for biomolecule sensing. In one aspect, a semiconductor chip comprises at least one field-effect transistor device which comprises a source, a drain, a gate stack and a channel region formed between the source and the drain. The gate stack only partially overlaps the channel region at the source side and/or at the drain side, such that a non-overlapped channel region at the source side and/or at the drain side is formed, where the non-overlapped channel region is configured for sensing biomolecules.

Abstract translation: 所公开的技术通常涉及半导体器件，更具体地涉及半导体器件，例如配置用于生物分子感测的场效晶体管器件。 一方面，半导体芯片包括至少一个场效应晶体管器件，其包括源极，漏极，栅极堆叠以及形成在源极和漏极之间的沟道区。 栅极堆叠仅部分地与源极侧和/或漏极侧的沟道区重叠，从而形成源极侧和/或在漏极侧的非重叠沟道区，其中非重叠沟道区 被配置用于感测生物分子。

公开(公告)号：US10211312B2

公开(公告)日：2019-02-19

申请号：US15230289

申请日：2016-08-05

Applicant: IMEC VZW

Inventor： Jan Van Houdt ,  Voon Yew Thean

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to a non-volatile ferroelectric memory device and to methods of fabricating the same. In one aspect, a non-volatile memory device includes a high dielectric constant layer (high-k) layer or a metal layer on a semiconductor substrate. The non-volatile memory device additionally includes a two-dimensional (2D) semiconductor channel layer interposed between the high-k layer or metal layer and a ferroelectric layer. The non-volatile memory device additionally includes a metal gate layer on the ferroelectric layer, and further includes a source region and a drain region each electrically coupled to the 2D semiconductor channel layer.

公开(公告)号：US20170040331A1

公开(公告)日：2017-02-09

申请号：US15230289

申请日：2016-08-05

Applicant: IMEC VZW

Inventor： Jan Van Houdt ,  Voon Yew Thean

IPC: H01L27/115 ,  H01L29/66 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/516 ,  H01L21/0242 ,  H01L21/02425 ,  H01L21/02568 ,  H01L21/28291 ,  H01L29/6684 ,  H01L29/78391

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to a non-volatile ferroelectric memory device and to methods of fabricating the same. In one aspect, a non-volatile memory device includes a high dielectric constant layer (high-k) layer or a metal layer on a semiconductor substrate. The non-volatile memory device additionally includes a two-dimensional (2D) semiconductor channel layer interposed between the high-k layer or metal layer and a ferroelectric layer. The non-volatile memory device additionally includes a metal gate layer on the ferroelectric layer, and further includes a source region and a drain region each electrically coupled to the 2D semiconductor channel layer.

Abstract translation: 所公开的技术通常涉及半导体器件，更具体地涉及非挥发性铁电存储器件及其制造方法。 一方面，非易失性存储器件包括半导体衬底上的高介电常数层（高k）层或金属层。 非易失性存储器件还包括插入在高k层或金属层与铁电层之间的二维（2D）半导体沟道层。 非易失性存储器件还包括在铁电层上的金属栅极层，并且还包括电源耦合到2D半导体沟道层的源极区域和漏极区域。

公开(公告)号：US09368498B2

公开(公告)日：2016-06-14

申请号：US14878012

申请日：2015-10-08

Applicant: IMEC VZW

Inventor： Geert Eneman ,  Benjamin Vincent ,  Voon Yew Thean

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78 ,  H01L21/8238

CPC classification number: H01L27/0886 ,  H01L21/823821 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7842 ,  H01L29/7849

Abstract: A FinFET device and a method for manufacturing a FinFET device is provided. An example device may comprise a substrate including at least two fin structures. Each of the at least two fin structures may be in contact with a source and drain region and each of the at least two fin structures may include a strain relaxed buffer (SRB) overlying and in contact with the substrate and an upper layer overlying and in contact with the SRB. The composition of the upper layer and the SRB may be selected such that the upper layer of a first fin structure is subjected to a first mobility enhancing strain in the as-grown state, the first mobility enhancing strain being applied in a longitudinal direction from the source region to the drain region and where at least an upper part of the upper layer of a second fin structure is strain-relaxed.