中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

12 records (took 0.018 seconds)

    MEMORY CELL
    1.
    发明公开
    MEMORY CELL 审中-公开

    公开(公告)号：US20240079051A1

    公开(公告)日：2024-03-07

    申请号：US17983331

    申请日：2022-11-08

    Applicant: Industrial Technology Research Institute

    Inventor： Chih-Sheng Lin ,  Tuo-Hung Hou ,  Fu-Cheng Tsai ,  Jian-Wei Su ,  Kuo-Hua Tseng

    IPC: G11C11/412 ,  G11C11/418

    CPC classification number: G11C11/412 ,  G11C11/418

    Abstract: Disclosed is a memory cell including a first transistor having a first terminal coupled to a bit line; a second transistor having a first terminal coupled to a bit line bar; a weight storage circuit coupled between a gate terminal of the first transistor and a gate terminal of the second transistor, storing a weight value, and determining to turn on the first transistor or the second transistor according to the weight value; and a driving circuit coupled to a second terminal of the first transistor, a second terminal of the second transistor, and at least one word line, receiving at least one threshold voltage and at least one input data from the word line, and determining whether to generate an operation current on a path of the turned-on first transistor or the turned-on second transistor according to the threshold voltage and the input data.

    MEMORY CIRCUIT WITH SENSE AMPLIFIER CALIBRATION MECHANISM
    2.
    发明公开
    MEMORY CIRCUIT WITH SENSE AMPLIFIER CALIBRATION MECHANISM 审中-公开

    公开(公告)号：US20230267973A1

    公开(公告)日：2023-08-24

    申请号：US18074528

    申请日：2022-12-05

    Applicant: Industrial Technology Research Institute

    Inventor： Chih-Sheng Lin ,  Fu-Cheng Tsai ,  Tuo-Hung Hou ,  Jian-Wei Su ,  Yu-Hui Lin ,  Chih-Ming Lai

    IPC: G11C7/06 ,  G11C7/12 ,  G11C7/10

    CPC classification number: G11C7/067 ,  G11C7/12 ,  G11C7/1063

    Abstract: According to an exemplary embodiments, the disclosure is directed to a memory circuit which includes not limited to a first half sense amplifier circuit connected to a first plurality of memory cells through a first bit line and configured to receive a unit of analog electrical signal from each of the first plurality of memory cells and to generate a first half sense amplifier output signal corresponding to the first bit line based on a first gain of the half sense amplifier and an accumulation of the units of analog signals, a locking code register circuit configured to receive a locking data and to generate a digital locking sequence, and a source selector circuit configured to receive the digital locking sequence and to generate a first adjustment signal to adjust the first half sense amplifier output signal corresponding to the first bit line by adjusting the first gain.

    COMPUTING IN MEMORY CELL
    3.
    发明公开
    COMPUTING IN MEMORY CELL 审中-公开

    公开(公告)号：US20230153375A1

    公开(公告)日：2023-05-18

    申请号：US18155762

    申请日：2023-01-18

    Applicant: Industrial Technology Research Institute

    Inventor： Chih-Sheng Lin ,  Jian-Wei Su ,  Tuo-Hung Hou ,  Sih-Han Li ,  Fu-Cheng Tsai ,  Yu-Hui Lin

    IPC: G06F17/16 ,  G11C11/412

    CPC classification number: G06F17/16 ,  G11C11/412

    Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, a third semiconductor element, and a fourth semiconductor element. A first terminal of the first semiconductor element receives a bias voltage. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to a first data node in the memory cell circuit. A second terminal of the third semiconductor element is adapted to receive a reference voltage. A control terminal of the third semiconductor element receives an inverted signal of the computing word-line. A first terminal of the fourth semiconductor element is coupled to a first computing bit-line. A second terminal of the fourth semiconductor element is coupled to a second computing bit-line.

    Memory circuit with sense amplifier calibration mechanism
    4.
    发明授权
    Memory circuit with sense amplifier calibration mechanism 有权

    公开(公告)号：US12142342B2

    公开(公告)日：2024-11-12

    申请号：US18074528

    申请日：2022-12-05

    Applicant: Industrial Technology Research Institute

    Inventor： Chih-Sheng Lin ,  Fu-Cheng Tsai ,  Tuo-Hung Hou ,  Jian-Wei Su ,  Yu-Hui Lin ,  Chih-Ming Lai

    IPC: G11C7/06 ,  G11C7/10 ,  G11C7/12

    Abstract: According to an exemplary embodiments, the disclosure is directed to a memory circuit which includes not limited to a first half sense amplifier circuit connected to a first plurality of memory cells through a first bit line and configured to receive a unit of analog electrical signal from each of the first plurality of memory cells and to generate a first half sense amplifier output signal corresponding to the first bit line based on a first gain of the half sense amplifier and an accumulation of the units of analog signals, a locking code register circuit configured to receive a locking data and to generate a digital locking sequence, and a source selector circuit configured to receive the digital locking sequence and to generate a first adjustment signal to adjust the first half sense amplifier output signal corresponding to the first bit line by adjusting the first gain.

    Computing in memory cell
    5.
    发明授权
    Computing in memory cell 有权

    公开(公告)号：US11599600B2

    公开(公告)日：2023-03-07

    申请号：US17013646

    申请日：2020-09-06

    Applicant: Industrial Technology Research Institute

    Inventor： Chih-Sheng Lin ,  Jian-Wei Su ,  Tuo-Hung Hou ,  Sih-Han Li ,  Fu-Cheng Tsai ,  Yu-Hui Lin

    IPC: G11C11/412 ,  G06F17/16

    Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, and a third semiconductor element. A first terminal of the first semiconductor element is coupled to a first computing bit-line. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to the memory cell circuit. A first terminal of the second semiconductor element is coupled to a second terminal of the first semiconductor element. A first terminal of the third semiconductor element is coupled to a second terminal of the second semiconductor element. A second terminal of the third semiconductor element is coupled to a second computing bit-line. A control terminal of the third semiconductor element receives a bias voltage.

    APPARATUS AND METHOD FOR NEURAL NETWORK COMPUTATION
    6.
    发明申请
    APPARATUS AND METHOD FOR NEURAL NETWORK COMPUTATION 有权

    公开(公告)号：US20210192327A1

    公开(公告)日：2021-06-24

    申请号：US17131783

    申请日：2020-12-23

    Applicant: Industrial Technology Research Institute

    Inventor： Sih-Han Li ,  Shih-Chieh Chang ,  Shyh-Shyuan Sheu ,  Jian-Wei Su ,  Fu-Cheng Tsai

    IPC: G06N3/063 ,  G06N3/04

    Abstract: An apparatus and a method for neural network computation are provided. The apparatus for neural network computation includes a first neuron circuit and a second neuron circuit. The first neuron circuit is configured to execute a neural network computation of at least one computing layer with a fixed feature pattern in a neural network algorithm. The second neuron circuit is configured to execute the neural network computation of at least one computing layer with an unfixed feature pattern in the neural network algorithm. The performance of the first neuron circuit is greater than that of the second neuron circuit.

    Computing in memory cell
    10.
    发明授权
    Computing in memory cell 有权

    公开(公告)号：US11741189B2

    公开(公告)日：2023-08-29

    申请号：US18155762

    申请日：2023-01-18

    Applicant: Industrial Technology Research Institute

    Inventor： Chih-Sheng Lin ,  Jian-Wei Su ,  Tuo-Hung Hou ,  Sih-Han Li ,  Fu-Cheng Tsai ,  Yu-Hui Lin

    IPC: G11C11/412 ,  G06F17/16

    CPC classification number: G06F17/16 ,  G11C11/412

    Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, a third semiconductor element, and a fourth semiconductor element. A first terminal of the first semiconductor element receives a bias voltage. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to a first data node in the memory cell circuit. A second terminal of the third semiconductor element is adapted to receive a reference voltage. A control terminal of the third semiconductor element receives an inverted signal of the computing word-line. A first terminal of the fourth semiconductor element is coupled to a first computing bit-line. A second terminal of the fourth semiconductor element is coupled to a second computing bit-line.

Patent Agency Ranking