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1.CHIP ARRANGEMENTS, A CHIP PACKAGE AND A METHOD FOR MANUFACTURING A CHIP ARRANGEMENT 有权
Title translation: 芯片安排,芯片封装和制造芯片布置的方法公开(公告)号:US20140097528A1
公开(公告)日:2014-04-10
申请号:US13645548
申请日:2012-10-05
Applicant: INFINEON TECHNOLOGIES AG
Inventor: Ralf Otremba , Josef Hoeglauer , Gerhard Noebauer , Chooi Mei Chong
IPC: H01L23/495 , H01L23/488 , H01L23/00
CPC classification number: H01L23/495 , H01L23/488 , H01L23/49524 , H01L23/49562 , H01L23/49575 , H01L24/03 , H01L24/29 , H01L24/32 , H01L24/37 , H01L24/40 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/84 , H01L24/92 , H01L2224/0603 , H01L2224/29101 , H01L2224/29298 , H01L2224/32245 , H01L2224/37111 , H01L2224/37118 , H01L2224/37124 , H01L2224/37139 , H01L2224/37144 , H01L2224/37147 , H01L2224/37155 , H01L2224/3716 , H01L2224/37164 , H01L2224/40095 , H01L2224/40137 , H01L2224/40245 , H01L2224/45014 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/49112 , H01L2224/49171 , H01L2224/73221 , H01L2224/73263 , H01L2224/73265 , H01L2224/83801 , H01L2224/8382 , H01L2224/84801 , H01L2224/8485 , H01L2224/92246 , H01L2224/92247 , H01L2924/00014 , H01L2924/0781 , H01L2924/12032 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/15701 , H01L2924/15717 , H01L2924/15724 , H01L2924/15738 , H01L2924/15747 , H01L2924/1576 , H01L2924/15763 , H01L2924/181 , H01L2924/00 , H01L2924/014 , H01L2224/45099
Abstract: A chip package is provided. The chip package includes a chip carrier, a voltage supply lead, a sensing terminal and a chip disposed over the chip carrier. The chip includes a first terminal and a second terminal, wherein the first terminal electrically contacts the chip carrier. The chip package also includes an electrically conductive element formed over the second terminal, the electrically conductive element electrically coupling the second terminal to the voltage supply lead and the sensing terminal.
Abstract translation: 提供芯片封装。 芯片封装包括芯片载体,电压源引线,感测端子和设置在芯片载体上的芯片。 芯片包括第一端子和第二端子,其中第一端子电接触芯片载体。 芯片封装还包括形成在第二端子上的导电元件,导电元件将第二端子电耦合到电压源引线和感测端子。
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2.Chip arrangements, a chip package and a method for manufacturing a chip arrangement 有权
Title translation: 芯片布置,芯片封装和芯片布置的制造方法公开(公告)号:US08853835B2
公开(公告)日:2014-10-07
申请号:US13645548
申请日:2012-10-05
Applicant: Infineon Technologies AG
Inventor: Ralf Otremba , Josef Hoeglauer , Gerhard Noebauer , Chooi Mei Chong
IPC: H01L23/495
CPC classification number: H01L23/495 , H01L23/488 , H01L23/49524 , H01L23/49562 , H01L23/49575 , H01L24/03 , H01L24/29 , H01L24/32 , H01L24/37 , H01L24/40 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/84 , H01L24/92 , H01L2224/0603 , H01L2224/29101 , H01L2224/29298 , H01L2224/32245 , H01L2224/37111 , H01L2224/37118 , H01L2224/37124 , H01L2224/37139 , H01L2224/37144 , H01L2224/37147 , H01L2224/37155 , H01L2224/3716 , H01L2224/37164 , H01L2224/40095 , H01L2224/40137 , H01L2224/40245 , H01L2224/45014 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/49112 , H01L2224/49171 , H01L2224/73221 , H01L2224/73263 , H01L2224/73265 , H01L2224/83801 , H01L2224/8382 , H01L2224/84801 , H01L2224/8485 , H01L2224/92246 , H01L2224/92247 , H01L2924/00014 , H01L2924/0781 , H01L2924/12032 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/15701 , H01L2924/15717 , H01L2924/15724 , H01L2924/15738 , H01L2924/15747 , H01L2924/1576 , H01L2924/15763 , H01L2924/181 , H01L2924/00 , H01L2924/014 , H01L2224/45099
Abstract: A chip package is provided. The chip package includes a chip carrier, a voltage supply lead, a sensing terminal and a chip disposed over the chip carrier. The chip includes a first terminal and a second terminal, wherein the first terminal electrically contacts the chip carrier. The chip package also includes an electrically conductive element formed over the second terminal, the electrically conductive element electrically coupling the second terminal to the voltage supply lead and the sensing terminal.
Abstract translation: 提供芯片封装。 芯片封装包括芯片载体,电压源引线,感测端子和设置在芯片载体上的芯片。 芯片包括第一端子和第二端子,其中第一端子电接触芯片载体。 芯片封装还包括形成在第二端子上的导电元件,导电元件将第二端子电耦合到电压源引线和感测端子。
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