公开(公告)号：US11088105B2

公开(公告)日：2021-08-10

申请号：US16695866

申请日：2019-11-26

Applicant: Infineon Technologies AG

Inventor： Thomas Bemmerl ,  Chooi Mei Chong ,  Edward Myers ,  Michael Stadler

IPC: H01L23/00

Abstract: A semiconductor device includes: a carrier having a die pad and a contact; a semiconductor die having opposing first and second main sides and being attached to the die pad by a first solder joint such that the second main side faces the die pad; and a contact clip having a first contact region and a second contact region. The first contact is attached to the first main side by a second solder joint. The second contact region is attached to the contact by a third solder joint. The first contact region has a convex shape facing towards the first main side such that a distance between the first main side and the first contact region increases from a base of the convex shape towards an edge of the first contact region. The base runs along a line that is substantially perpendicular to a longitudinal axis of the contact clip.

公开(公告)号：US08853835B2

公开(公告)日：2014-10-07

申请号：US13645548

申请日：2012-10-05

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Josef Hoeglauer ,  Gerhard Noebauer ,  Chooi Mei Chong

IPC: H01L23/495

CPC classification number: H01L23/495 ,  H01L23/488 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/03 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/84 ,  H01L24/92 ,  H01L2224/0603 ,  H01L2224/29101 ,  H01L2224/29298 ,  H01L2224/32245 ,  H01L2224/37111 ,  H01L2224/37118 ,  H01L2224/37124 ,  H01L2224/37139 ,  H01L2224/37144 ,  H01L2224/37147 ,  H01L2224/37155 ,  H01L2224/3716 ,  H01L2224/37164 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40245 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49112 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8382 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/0781 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15701 ,  H01L2924/15717 ,  H01L2924/15724 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/15763 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/45099

Abstract: A chip package is provided. The chip package includes a chip carrier, a voltage supply lead, a sensing terminal and a chip disposed over the chip carrier. The chip includes a first terminal and a second terminal, wherein the first terminal electrically contacts the chip carrier. The chip package also includes an electrically conductive element formed over the second terminal, the electrically conductive element electrically coupling the second terminal to the voltage supply lead and the sensing terminal.

Abstract translation: 提供芯片封装。 芯片封装包括芯片载体，电压源引线，感测端子和设置在芯片载体上的芯片。 芯片包括第一端子和第二端子，其中第一端子电接触芯片载体。 芯片封装还包括形成在第二端子上的导电元件，导电元件将第二端子电耦合到电压源引线和感测端子。

公开(公告)号：US11869865B2

公开(公告)日：2024-01-09

申请号：US17389721

申请日：2021-07-30

Applicant: Infineon Technologies AG

Inventor： Thomas Bemmerl ,  Chooi Mei Chong ,  Edward Myers ,  Michael Stadler

IPC: H01L23/00

CPC classification number: H01L24/37 ,  H01L24/84 ,  H01L2224/37012 ,  H01L2224/84345 ,  H01L2224/84815 ,  H01L2924/3656

Abstract: A semiconductor device includes: a carrier having a die pad and a contact; a semiconductor die having opposing first and second main sides and being attached to the die pad by a first solder joint such that the second main side faces the die pad; and a contact clip having a first contact region and a second contact region. The first contact is attached to the first main side by a second solder joint. The second contact region is attached to the contact by a third solder joint. The first contact region has a convex shape facing towards the first main side such that a distance between the first main side and the first contact region increases from a base of the convex shape towards an edge of the first contact region. The base runs along a line that is substantially perpendicular to a longitudinal axis of the contact clip.

公开(公告)号：US11211356B2

公开(公告)日：2021-12-28

申请号：US16991123

申请日：2020-08-12

Applicant: Infineon Technologies AG

Inventor： Wee Aun Jason Lim ,  Paul Armand Asentista Calo ,  Ting Soon Chin ,  Chooi Mei Chong ,  Sanjay Kumar Murugan ,  Ying Pok Sam ,  Chee Voon Tan

IPC: H01L23/495 ,  H01L23/28 ,  H01L21/00 ,  H05K7/18 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

Abstract: A power semiconductor package includes a power semiconductor chip, an electrical connector arranged at a first side of the power semiconductor chip and having a first surface that is coupled to a power electrode of the power semiconductor chip, an encapsulation body at least partially encapsulating the power semiconductor chip and the electrical connector, and an electrical insulation layer arranged at a second surface of the electrical connector opposite the first surface, wherein parts of the encapsulation body and the electrical insulation layer form a coplanar surface of the power semiconductor package.

公开(公告)号：US20210358877A1

公开(公告)日：2021-11-18

申请号：US17389721

申请日：2021-07-30

Applicant: Infineon Technologies AG

Inventor： Thomas Bemmerl ,  Chooi Mei Chong ,  Edward Myers ,  Michael Stadler

IPC: H01L23/00

Abstract: A semiconductor device includes: a carrier having a die pad and a contact; a semiconductor die having opposing first and second main sides and being attached to the die pad by a first solder joint such that the second main side faces the die pad; and a contact clip having a first contact region and a second contact region. The first contact is attached to the first main side by a second solder joint. The second contact region is attached to the contact by a third solder joint. The first contact region has a convex shape facing towards the first main side such that a distance between the first main side and the first contact region increases from a base of the convex shape towards an edge of the first contact region. The base runs along a line that is substantially perpendicular to a longitudinal axis of the contact clip.

公开(公告)号：US20200168575A1

公开(公告)日：2020-05-28

申请号：US16695866

申请日：2019-11-26

Applicant: Infineon Technologies AG

Inventor： Thomas Bemmerl ,  Chooi Mei Chong ,  Edward Myers ,  Michael Stadler

IPC: H01L23/00

Abstract: A semiconductor device includes: a carrier having a die pad and a contact; a semiconductor die having opposing first and second main sides and being attached to the die pad by a first solder joint such that the second main side faces the die pad; and a contact clip having a first contact region and a second contact region. The first contact is attached to the first main side by a second solder joint. The second contact region is attached to the contact by a third solder joint. The first contact region has a convex shape facing towards the first main side such that a distance between the first main side and the first contact region increases from a base of the convex shape towards an edge of the first contact region. The base runs along a line that is substantially perpendicular to a longitudinal axis of the contact clip.

公开(公告)号：US20210057375A1

公开(公告)日：2021-02-25

申请号：US16991123

申请日：2020-08-12

Applicant: Infineon Technologies AG

Inventor： Wee Aun Jason Lim ,  Paul Armand Asentista Calo ,  Ting Soon Chin ,  Chooi Mei Chong ,  Sanjay Kumar Murugan ,  Ying Pok Sam ,  Chee Voon Tan

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/495

Abstract: A power semiconductor package includes a power semiconductor chip, an electrical connector arranged at a first side of the power semiconductor chip and having a first surface that is coupled to a power electrode of the power semiconductor chip, an encapsulation body at least partially encapsulating the power semiconductor chip and the electrical connector, and an electrical insulation layer arranged at a second surface of the electrical connector opposite the first surface, wherein parts of the encapsulation body and the electrical insulation layer form a coplanar surface of the power semiconductor package.

公开(公告)号：US10147703B2

公开(公告)日：2018-12-04

申请号：US15469112

申请日：2017-03-24

Applicant: Infineon Technologies AG

Inventor： Stefan Macheiner ,  Amirul Afiq Hud ,  Teck Sim Lee ,  Thomas Stoek ,  Lee Shuang Wang ,  Chooi Mei Chong ,  Wei Hing Tan

IPC: H01L23/52 ,  H01L25/065 ,  H01L23/498 ,  H01L23/538 ,  H01L23/057 ,  H01L25/00 ,  H01L29/78

Abstract: In some examples, a device includes a power supply element and a reference voltage element, wherein the reference voltage element is electrically isolated from the power supply element. The device further includes a high-side semiconductor die including at least two high-side transistors, wherein each high-side transistor of the at least two high-side transistors is electrically connected to the power supply element. The device also includes a low-side semiconductor die including at least two low-side transistors, wherein each low-side transistor of the at least two low-side transistors is electrically connected to the reference voltage element. The device includes at least two switching elements, wherein each switching element of the at least two switching elements is electrically connected to a respective high-side transistor of the at least two high-side transistors and to a respective low-side transistor of the at least two low-side transistors.

公开(公告)号：US20140097528A1

公开(公告)日：2014-04-10

申请号：US13645548

申请日：2012-10-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Ralf Otremba ,  Josef Hoeglauer ,  Gerhard Noebauer ,  Chooi Mei Chong

IPC: H01L23/495 ,  H01L23/488 ,  H01L23/00

CPC classification number: H01L23/495 ,  H01L23/488 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/03 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/84 ,  H01L24/92 ,  H01L2224/0603 ,  H01L2224/29101 ,  H01L2224/29298 ,  H01L2224/32245 ,  H01L2224/37111 ,  H01L2224/37118 ,  H01L2224/37124 ,  H01L2224/37139 ,  H01L2224/37144 ,  H01L2224/37147 ,  H01L2224/37155 ,  H01L2224/3716 ,  H01L2224/37164 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40245 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49112 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8382 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/0781 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15701 ,  H01L2924/15717 ,  H01L2924/15724 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/15763 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/45099

Abstract: A chip package is provided. The chip package includes a chip carrier, a voltage supply lead, a sensing terminal and a chip disposed over the chip carrier. The chip includes a first terminal and a second terminal, wherein the first terminal electrically contacts the chip carrier. The chip package also includes an electrically conductive element formed over the second terminal, the electrically conductive element electrically coupling the second terminal to the voltage supply lead and the sensing terminal.

Abstract translation: 提供芯片封装。 芯片封装包括芯片载体，电压源引线，感测端子和设置在芯片载体上的芯片。 芯片包括第一端子和第二端子，其中第一端子电接触芯片载体。 芯片封装还包括形成在第二端子上的导电元件，导电元件将第二端子电耦合到电压源引线和感测端子。

公开(公告)号：US20180277513A1

公开(公告)日：2018-09-27

申请号：US15469112

申请日：2017-03-24

Applicant: Infineon Technologies AG

Inventor： Stefan Macheiner ,  Amirul Afiq Hud ,  Teck Sim Lee ,  Thomas Stoek ,  Lee Shuang Wang ,  Chooi Mei Chong ,  Wei Hing Tan

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/538 ,  H01L23/057 ,  H01L25/00

CPC classification number: H01L25/0655 ,  H01L23/057 ,  H01L23/49805 ,  H01L23/49844 ,  H01L23/5386 ,  H01L25/50 ,  H01L29/7827

Abstract: In some examples, a device includes a power supply element and a reference voltage element, wherein the reference voltage element is electrically isolated from the power supply element. The device further includes a high-side semiconductor die including at least two high-side transistors, wherein each high-side transistor of the at least two high-side transistors is electrically connected to the power supply element. The device also includes a low-side semiconductor die including at least two low-side transistors, wherein each low-side transistor of the at least two low-side transistors is electrically connected to the reference voltage element. The device includes at least two switching elements, wherein each switching element of the at least two switching elements is electrically connected to a respective high-side transistor of the at least two high-side transistors and to a respective low-side transistor of the at least two low-side transistors.