公开(公告)号：US11249910B2

公开(公告)日：2022-02-15

申请号：US16717647

申请日：2019-12-17

Applicant: Intel Corporation

Inventor： Aravindh Anantaraman ,  Srinivas Sridharan ,  Ajaya Durg ,  Mohammad R. Haghighat ,  Mikhail E. Smorkalov ,  Sudarshan Srinivasan

IPC: G06F12/08 ,  G06F3/06 ,  G06F12/0868 ,  G06F12/10 ,  G06F16/2455 ,  G06N3/08 ,  G06F12/0877 ,  G06F12/0871

Abstract: Systems, apparatuses and methods may provide for technology that detects a runtime call to a communication library, wherein the runtime call identifies a memory buffer, determines that a class of service (CLOS) attribute is associated with the memory buffer, and issues a driver instruction to modify the CLOS attribute in response to the runtime call.

公开(公告)号：US12190405B2

公开(公告)日：2025-01-07

申请号：US17853711

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Todd Rimmer ,  Mark Debbage ,  Bruce G. Warren ,  Sayantan Sur ,  Nayan Amrutlal Suthar ,  Ajaya Durg

IPC: G06T1/60 ,  G06T1/20

Abstract: Examples described herein relate to a first graphics processing unit (GPU) with at least one integrated communications system, wherein the at least one integrated communications system is to apply a reliability protocol to communicate with a second at least one integrated communications system associated with a second GPU to copy data from a first memory region to a second memory region and wherein the first memory region is associated with the first GPU and the second memory region is associated with the second GPU.

公开(公告)号：US12229069B2

公开(公告)日：2025-02-18

申请号：US17083200

申请日：2020-10-28

Applicant: Intel Corporation

Inventor： Pratik Marolia ,  Andrew Herdrich ,  Rajesh Sankaran ,  Rahul Pal ,  David Puffer ,  Sayantan Sur ,  Ajaya Durg

IPC: G06F13/40 ,  G06F13/42

Abstract: Methods and apparatus for an accelerator controller hub (ACH). The ACH may be a stand-alone component or integrated on-die or on package in an accelerator such as a GPU. The ACH may include a host device link (HDL) interface, one or more Peripheral Component Interconnect Express (PCIe) interfaces, one or more high performance accelerator link (HPAL) interfaces, and a router, operatively coupled to each of the HDL interface, the one or more PCIe interfaces, and the one or more HPAL interfaces. The HDL interface is configured to be coupled to a host CPU via an HDL link and the one or more HPAL interfaces are configured to be coupled to one or more HPALs that are used to access high performance accelerator fabrics (HPAFs) such as NVlink fabrics and CCIX (Cache Coherent Interconnect for Accelerators) fabrics. Platforms including ACHs or accelerators with integrated ACHs support RDMA transfers using RDMA semantics to enable transfers between accelerator memory on initiators and targets without CPU involvement.

公开(公告)号：US20210200678A1

公开(公告)日：2021-07-01

申请号：US16939197

申请日：2020-07-27

Applicant: Intel Corporation

Inventor： Rahul Pal ,  Philip Abraham ,  Ajaya Durg ,  Bahaa Fahim ,  Yen-Cheng Liu ,  Sanilkumar Mm

IPC: G06F12/0815 ,  G06F12/0893 ,  G06F11/10

Abstract: A processor, including a core; and a cache-coherent memory fabric coupled to the core and having a primary cache agent (PCA) configured to provide a primary access path; and a secondary cache agent (SCA) configured to provide a secondary access path that is redundant to the primary access path, wherein the PCA has a coherency controller configured to maintain data in the secondary access path coherent with data in the main access path.

公开(公告)号：US11604730B2

公开(公告)日：2023-03-14

申请号：US16939197

申请日：2020-07-27

Applicant: Intel Corporation

Inventor： Rahul Pal ,  Philip Abraham ,  Ajaya Durg ,  Bahaa Fahim ,  Yen-Cheng Liu ,  Sanilkumar Mm

IPC: G06F12/08 ,  G06F12/0815 ,  G06F11/10 ,  G06F12/0893

Abstract: A processor, including a core; and a cache-coherent memory fabric coupled to the core and having a primary cache agent (PCA) configured to provide a primary access path; and a secondary cache agent (SCA) configured to provide a secondary access path that is redundant to the primary access path, wherein the PCA has a coherency controller configured to maintain data in the secondary access path coherent with data in the main access path.

公开(公告)号：US20220351326A1

公开(公告)日：2022-11-03

申请号：US17853711

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Todd RIMMER ,  Mark DEBBAGE ,  Bruce G. WARREN ,  Sayantan SUR ,  Nayan Amrutlal SUTHAR ,  Ajaya Durg

IPC: G06T1/20 ,  G06T1/60

Abstract: Examples described herein relate to a first graphics processing unit (GPU) with at least one integrated communications system, wherein the at least one integrated communications system is to apply a reliability protocol to communicate with a second at least one integrated communications system associated with a second GPU to copy data from a first memory region to a second memory region and wherein the first memory region is associated with the first GPU and the second memory region is associated with the second GPU.

公开(公告)号：US09698781B1

公开(公告)日：2017-07-04

申请号：US15165501

申请日：2016-05-26

Applicant: INTEL CORPORATION

Inventor： Arojit Roychowdhury ,  Ajaya Durg ,  Shilpa Huddar ,  Sunil Shanbhag ,  Vishram Sarurkar ,  Tejpal Singh

IPC: H03K19/00

CPC classification number: H03K19/0016

Abstract: An electronic apparatus may be provided that includes a clock device to provide a clock signal, and a clock gate to receive the clock signal, the clock gate to be selectively provided in an enabled state or a disabled state. The electronic apparatus may also include a controller to determine a frequency transition and to control the clock gate to be in the enabled state or the disabled state based on the determined frequency transition.