FAST-LANE ROUTING FOR MULTI-CHIP PACKAGES
    3.
    发明申请

    公开(公告)号:US20200067816A1

    公开(公告)日:2020-02-27

    申请号:US16106926

    申请日:2018-08-21

    Abstract: Embodiments herein may relate to a processor package with a substrate and a multi-chip processor coupled with the substrate. The multi-chip processor may include a dual-sided interconnect structure coupled with a first chip, a second chip, and a third chip. The first chip may be communicatively coupled with the second chip by an on-chip communication route. Likewise, the second chip may be communicatively coupled with the first chip by an on-chip communication route. Additionally, the first chip may be communicatively coupled with the third chip by a fast-lane communication route. Other embodiments may be described and/or claimed.

    Fast-lane routing for multi-chip packages

    公开(公告)号:US11336559B2

    公开(公告)日:2022-05-17

    申请号:US16106926

    申请日:2018-08-21

    Abstract: Embodiments herein may relate to a processor package with a substrate and a multi-chip processor coupled with the substrate. The multi-chip processor may include a dual-sided interconnect structure coupled with a first chip, a second chip, and a third chip. The first chip may be communicatively coupled with the second chip by an on-chip communication route. Likewise, the second chip may be communicatively coupled with the first chip by an on-chip communication route. Additionally, the first chip may be communicatively coupled with the third chip by a fast-lane communication route. Other embodiments may be described and/or claimed.

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