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公开(公告)号:US20230197676A1
公开(公告)日:2023-06-22
申请号:US17557166
申请日:2021-12-21
Applicant: Intel Corporation
Inventor: Gerald S. Pasdast , Adel A. Elsherbini , Nevine Nassif , Carleton L. Molnar , Vivek Kumar Rajan , Peipei Wang , Shawna M. Liff , Tejpal Singh , Johanna M. Swan
IPC: H01L25/065 , H01L23/498
CPC classification number: H01L25/0652 , H01L23/49827 , H01L23/49894 , H01L23/49838
Abstract: A microelectronic assembly is provided, comprising: a first integrated circuit (IC) die having a first connection to a first serializer/deserializer (SERDES) circuit and a second connection to a second SERDES circuit; a second IC die having the first SERDES circuit; and a third IC die having the second SERDES circuit, in which the first IC die is in a first layer, the second IC die and the third IC die are in a second layer not coplanar with the first layer, the first layer and the second layer are coupled by interconnects having a pitch of less than 10 micrometers between adjacent ones of the interconnects, and the first SERDES circuit and the second SERDES circuit are coupled by a conductive pathway.
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公开(公告)号:US11294852B2
公开(公告)日:2022-04-05
申请号:US16917888
申请日:2020-06-30
Applicant: Intel Corporation
Inventor: Nevine Nassif , Yen-Cheng Liu , Krishnakanth V. Sistla , Gerald Pasdast , Siva Soumya Eachempati , Tejpal Singh , Ankush Varma , Mahesh K. Kumashikar , Srikanth Nimmagadda , Carleton L. Molnar , Vedaraman Geetha , Jeffrey D. Chamberlain , William R. Halleck , George Z. Chrysos , John R. Ayers , Dheeraj R. Subbareddy
IPC: G06F1/04 , G06F15/78 , G06F1/10 , G06F15/167 , G06F9/38 , G06F9/50 , G06F15/173
Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.
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公开(公告)号:US20200067816A1
公开(公告)日:2020-02-27
申请号:US16106926
申请日:2018-08-21
Applicant: Intel Corporation
Inventor: Adel A. Elsherbini , Tejpal Singh , Shawna M. Liff , Gerald S. Pasdast , Johanna M. Swan
IPC: H04L12/733 , H04L12/933 , G06F12/0842 , H04L29/06
Abstract: Embodiments herein may relate to a processor package with a substrate and a multi-chip processor coupled with the substrate. The multi-chip processor may include a dual-sided interconnect structure coupled with a first chip, a second chip, and a third chip. The first chip may be communicatively coupled with the second chip by an on-chip communication route. Likewise, the second chip may be communicatively coupled with the first chip by an on-chip communication route. Additionally, the first chip may be communicatively coupled with the third chip by a fast-lane communication route. Other embodiments may be described and/or claimed.
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公开(公告)号:US10795853B2
公开(公告)日:2020-10-06
申请号:US15721822
申请日:2017-09-30
Applicant: Intel Corporation
Inventor: Nevine Nassif , Yen-Cheng Liu , Krishnakanth V. Sistla , Gerald Pasdast , Siva Soumya Eachempati , Tejpal Singh , Ankush Varma , Mahesh K. Kumashikar , Srikanth Nimmagadda , Carleton L. Molnar , Vedaraman Geetha , Jeffrey D. Chamberlain , William R. Halleck , George Z. Chrysos , John R. Ayers , Dheeraj R. Subbareddy
IPC: G06F1/04 , G06F1/12 , G06F5/06 , G06F15/78 , G06F1/10 , G06F15/167 , G06F9/38 , G06F9/50 , G06F15/173
Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.
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公开(公告)号:US11899615B2
公开(公告)日:2024-02-13
申请号:US18102568
申请日:2023-01-27
Applicant: Intel Corporation
Inventor: Nevine Nassif , Yen-Cheng Liu , Krishnakanth V. Sistla , Gerald Pasdast , Siva Soumya Eachempati , Tejpal Singh , Ankush Varma , Mahesh K. Kumashikar , Srikanth Nimmagadda , Carleton L. Molnar , Vedaraman Geetha , Jeffrey D. Chamberlain , William R. Halleck , George Z Chrysos , John R. Ayers , Dheeraj R. Subbareddy
IPC: G06F1/00 , G06F15/78 , G06F1/10 , G06F15/167 , G06F1/04 , G06F1/12 , G06F9/38 , G06F9/50 , G06F15/173
CPC classification number: G06F15/7889 , G06F1/04 , G06F1/10 , G06F1/12 , G06F9/3869 , G06F9/5038 , G06F15/167 , G06F15/17312
Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.
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公开(公告)号:US10193826B2
公开(公告)日:2019-01-29
申请号:US14800552
申请日:2015-07-15
Applicant: INTEL CORPORATION
Inventor: Bahaa Fahim , Yen-Cheng Liu , Chung-Chi Wang , Donald C. Soltis, Jr. , Terry C. Huang , Tejpal Singh , Bongjin Jung , Nazar Syed Haider
IPC: H04L12/933 , H04L12/937 , G06F13/40 , G06F11/10
Abstract: A shared mesh comprises a mesh station. The mesh station is used to couple to at least a first core component and a second core component. The mesh station includes a logic unit. The mesh station is shared by at least the first core component and the second core component. A memory is coupled to the mesh station.
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公开(公告)号:US11336559B2
公开(公告)日:2022-05-17
申请号:US16106926
申请日:2018-08-21
Applicant: Intel Corporation
Inventor: Adel A. Elsherbini , Tejpal Singh , Shawna M. Liff , Gerald S. Pasdast , Johanna M. Swan
IPC: H04L45/122 , H04L45/12 , H04L9/40 , G06F12/0842 , H04L49/109
Abstract: Embodiments herein may relate to a processor package with a substrate and a multi-chip processor coupled with the substrate. The multi-chip processor may include a dual-sided interconnect structure coupled with a first chip, a second chip, and a third chip. The first chip may be communicatively coupled with the second chip by an on-chip communication route. Likewise, the second chip may be communicatively coupled with the first chip by an on-chip communication route. Additionally, the first chip may be communicatively coupled with the third chip by a fast-lane communication route. Other embodiments may be described and/or claimed.
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公开(公告)号:US11256657B2
公开(公告)日:2022-02-22
申请号:US16364619
申请日:2019-03-26
Applicant: Intel Corporation
Inventor: Tejpal Singh , Yedidya Hilewitz , Ankush Varma , Yen-Cheng Liu , Krishnakanth V. Sistla , Jeffrey Chamberlain
IPC: G06F15/00 , G06F15/76 , G06F15/78 , G06F9/54 , G06F9/30 , G06F1/3296 , G06F1/3234
Abstract: In one embodiment, an apparatus includes an interconnect to couple a plurality of processing circuits. The interconnect may include a pipe stage circuit coupled between a first processing circuit and a second processing circuit. This pipe stage circuit may include: a pipe stage component having a first input to receive a signal via the interconnect and a first output to output the signal; and a selection circuit having a first input to receive the signal from the first output of the pipe stage component and a second input to receive the signal via a bypass path, where the selection circuit is dynamically controllable to output the signal received from the first output of the pipe stage component or the signal received via the bypass path. Other embodiments are described and claimed.
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公开(公告)号:US11734174B2
公开(公告)日:2023-08-22
申请号:US16576687
申请日:2019-09-19
Applicant: Intel Corporation
Inventor: Huichu Liu , Tanay Karnik , Tejpal Singh , Yen-Cheng Liu , Lavanya Subramanian , Mahesh Kumashikar , Sri Harsha Choday , Sreenivas Subramoney , Kaushik Vaidyanathan , Daniel H. Morris , Uygar E. Avci , Ian A. Young
IPC: G06F12/08 , G06F12/0804 , G06F12/0866 , G06F12/0806 , G06F11/20
CPC classification number: G06F12/0804 , G06F11/2089 , G06F12/0806 , G06F12/0866
Abstract: Described is an low overhead method and apparatus to reconfigure a pair of buffered interconnect links to operate in one of these three modes—first mode (e.g., bandwidth mode), second mode (e.g., latency mode), and third mode (e.g., energy mode). In bandwidth mode, each link in the pair buffered interconnect links carries a unique signal from source to destination. In latency mode, both links in the pair carry the same signal from source to destination, where one link in the pair is “primary” and other is called the “assist”. Temporal alignment of transitions in this pair of buffered interconnects reduces the effective capacitance of primary, thereby reducing delay or latency. In energy mode, one link in the pair, the primary, alone carries a signal, while the other link in the pair is idle. An idle neighbor on one side reduces energy consumption of the primary.
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公开(公告)号:US11586579B2
公开(公告)日:2023-02-21
申请号:US17513795
申请日:2021-10-28
Applicant: Intel Corporation
Inventor: Nevine Nassif , Yen-Cheng Liu , Krishnakanth V. Sistla , Gerald Pasdast , Siva Soumya Eachempati , Tejpal Singh , Ankush Varma , Mahesh K. Kumashikar , Srikanth Nimmagadda , Carleton L. Molnar , Vedaraman Geetha , Jeffrey D. Chamberlain , William R. Halleck , George Z. Chrysos , John R. Ayers , Dheeraj R. Subbareddy
IPC: G06F1/04 , G06F1/12 , G06F15/78 , G06F1/10 , G06F15/167 , G06F9/38 , G06F9/50 , G06F15/173
Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.
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