公开(公告)号：US10824356B2

公开(公告)日：2020-11-03

申请号：US15977335

申请日：2018-05-11

Applicant: Intel Corporation

Inventor： Jawad Khan ,  Akshay Pethe

IPC: G06F3/06 ,  G06F12/02

Abstract: A semiconductor apparatus may include technology to identify two or more types of storage controller traffic, direct a first identified type of storage controller traffic along a fixed processing path, and direct a second type of storage controller traffic along a programmable processing path. Other embodiments are disclosed and claimed.

公开(公告)号：US20190042132A1

公开(公告)日：2019-02-07

申请号：US15977335

申请日：2018-05-11

Applicant: Intel Corporation

Inventor： Jawad Khan ,  Akshay Pethe

IPC: G06F3/06

Abstract: A semiconductor apparatus may include technology to identify two or more types of storage controller traffic, direct a first identified type of storage controller traffic along a fixed processing path, and direct a second type of storage controller traffic along a programmable processing path. Other embodiments are disclosed and claimed.

公开(公告)号：US20170235701A1

公开(公告)日：2017-08-17

申请号：US15503097

申请日：2014-12-24

Applicant: INTEL CORPORATION

Inventor： Akshay Pethe ,  Mahesh Wagh ,  David Harriman ,  Su Wei Lim ,  Debendra Das Sharma ,  Daniel Froelich ,  Venkatraman Iyer ,  James Jaussi ,  Zuoguo Wu

IPC: G06F13/42 ,  G06F13/38

CPC classification number: G06F13/4286 ,  G06F13/385 ,  G06F13/4027 ,  G06F2213/0042 ,  G06F2213/4002

Abstract: Techniques for embedded high speed serial interface methods are described herein. The techniques include an apparatus for sideband signaling including a first serial sideband link module and a second serial sideband link module. The first serial sideband link module is to propagate packets from an upstream port to a downstream port via a first signaling lane, and the second serial sideband link module is to propagate packets from the downstream port to the upstream port via a second signaling lane.