公开(公告)号：US11016549B2

公开(公告)日：2021-05-25

申请号：US15870629

申请日：2018-01-12

Applicant: Intel Corporation

Inventor： Poh Thiam Teoh ,  Mikal C. Hunsaker ,  Su Wei Lim ,  Gim Chong Lee ,  Hooi Kar Loo ,  Shashitheren Kerisnan ,  Siang Lin Tan ,  Ming Chew Lee ,  Ngeok Kuan Wai ,  Li Len Lim

IPC: G06F1/26 ,  G06F1/10 ,  G06F13/42

Abstract: Aspects of the embodiments are directed to systems, methods, and apparatuses for controlling power management states using a clock request message across a 3.3 volt GPIO pin. Systems can include a CPU root port to transmit to a platform controller hub (PCH) compliant with a PCIe protocol, a first clock request message, the first clock request message comprising a first bit set to assert a clock request transmit (CLKREQ TX assert) on a 3.3 volt general purpose input/output (GPIO) pin local to the PCH; detect that a connected device is entering into a power management state; and transmit, from the CPU root port, to the PCH, a second clock request message, the second clock request message comprising the first bit set to deassert the clock request transmit (CLKREQ TX deassert) and a second bit to assert a clock request protocol (CLKREQ#) on a 3.3 volt GPIO pin.

公开(公告)号：US20190303338A1

公开(公告)日：2019-10-03

申请号：US16266992

申请日：2019-02-04

Applicant: Intel Corporation

Inventor： Michelle Jen ,  Daniel Froelich ,  Debendra Das Sharma ,  Bruce Tennant ,  Quinn Devine ,  Su Wei Lim

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/38

Abstract: An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.

公开(公告)号：US20190229901A1

公开(公告)日：2019-07-25

申请号：US16368800

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Reouven Elbaz ,  Hooi Kar Loo ,  Poh Thiam Teoh ,  Su Wei Lim ,  Patrick D. Maloney ,  Santosh Ghosh

IPC: H04L9/08 ,  H04L9/12 ,  G06F13/42

Abstract: Methods, systems, and apparatuses associated with hardware mechanisms for link encryption are disclosed. In various embodiments, an interconnect interface is coupled to a processor core to interconnect a peripheral device to the processor core via a link established between the peripheral device and the interconnect interface. The interconnect interface is to select a cryptographic engine of a plurality of cryptographic engines instantiated in the interconnect interface for the link. The cryptographic engine is to symmetrically encrypt data to be transmitted through the link. In more specific embodiments, each of the plurality of cryptographic engines is instantiated for one of a request type on the link, a virtual channel on the link, or a request type within a virtual channel on the link.

公开(公告)号：US10248183B2

公开(公告)日：2019-04-02

申请号：US15370507

申请日：2016-12-06

Applicant: Intel Corporation

Inventor： Jennifer Chin ,  Su Wei Lim ,  Poh Thiam Teoh ,  Ting Lok Song ,  Sun Zheng E ,  Say Cheong Gan ,  Sujea Lim ,  Ming Yi Lim

IPC: G06F1/32 ,  G06F1/3287 ,  G06F1/16 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3218 ,  G06F13/42

Abstract: Particular embodiments described herein can offer a method for managing power for at least one processor that includes evaluating a plurality of ports associated with an electronic device; determining that a particular pin associated with at least one of the ports is not receiving a signal; disabling a squelch function associated with the electronic device; and gating power associated with a physical layer (PHY) of the electronic device.

公开(公告)号：US09124455B1

公开(公告)日：2015-09-01

申请号：US14495768

申请日：2014-09-24

Applicant: INTEL CORPORATION

Inventor： Su Wei Lim ,  Ronald W. Swartz ,  Yueming Jiang ,  Hooi Kar Loo ,  Athourina Gevergiz ,  Bruce A. Tennant ,  Yick Yaw Ho ,  Poh Thiam Teoh ,  Jennifer Chin ,  Hui Shi

IPC: H03H7/30 ,  H04L25/03

CPC classification number: H04L25/03885 ,  H04L25/03343 ,  H04L2025/03681

Abstract: Techniques for embedded high speed serial interface methods are described herein. The techniques provide an apparatus for link equalization including an equalization control module to determine at least a first coefficient setting and a second coefficient setting at a remote transmitter based on an algorithm. The apparatus also includes a receiver margining module to determine a first margin value to be associated with the first coefficient setting and a second margin value to be associated with the second coefficient setting. The receiver margining module is to further determine if at least the first margin value is higher than the second margin value.

Abstract translation: 本文描述了嵌入式高速串行接口方法的技术。 这些技术提供了一种用于链路均衡的装置，包括均衡控制模块，用于基于算法确定在远程发射机处的至少第一系数设置和第二系数设置。 该装置还包括接收器边界模块，用于确定与第一系数设置相关联的第一边距值和与第二系数设置相关联的第二边距值。 接收器余量模块用于进一步确定至少第一边际值是否高于第二边际值。

公开(公告)号：US20230026906A1

公开(公告)日：2023-01-26

申请号：US17819390

申请日：2022-08-12

Applicant: Intel Corporation

Inventor： Joon Teik Hor ,  Ting Lok Song ,  Mahesh Wagh ,  Su Wei Lim

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

Abstract: In one embodiment, an apparatus includes an arbitration circuit with virtual link state machines to virtualize link states associated with multiple communication protocol stacks. The apparatus further includes a physical circuit coupled to the arbitration circuit and to interface with a physical link, where the physical circuit, in response to a retraining of the physical link, is to cause a plurality of the virtual link state machines to synchronize with corresponding virtual link state machines associated with a second side of the physical link, and where at least one of the communication protocol stacks is to remain in a low power state during the retraining and the synchronization. Other embodiments are described and claimed.

公开(公告)号：US20220350769A1

公开(公告)日：2022-11-03

申请号：US17721413

申请日：2022-04-15

Applicant: Intel Corporation

Inventor： Joon Teik Hor ,  Ting Lok Song ,  Mahesh Wagh ,  Su Wei Lim

IPC: G06F13/40 ,  G06F13/38 ,  G06F13/42 ,  G06F13/16

Abstract: Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.

公开(公告)号：US11308018B2

公开(公告)日：2022-04-19

申请号：US17015963

申请日：2020-09-09

Applicant: Intel Corporation

Inventor： Joon Teik Hor ,  Ting Lok Song ,  Mahesh Wagh ,  Su Wei Lim

IPC: G06F13/40 ,  G06F13/38 ,  G06F13/42 ,  G06F13/16

Abstract: Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.

公开(公告)号：US20190227972A1

公开(公告)日：2019-07-25

申请号：US16373472

申请日：2019-04-02

Applicant: Intel Corporation

Inventor： Joon Teik Hor ,  Ting Lok Song ,  Mahesh Wagh ,  Su Wei Lim

IPC: G06F13/40 ,  G06F13/16 ,  G06F13/42 ,  G06F13/38

Abstract: Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.

公开(公告)号：US10209911B2

公开(公告)日：2019-02-19

申请号：US15024717

申请日：2014-09-16

Applicant: INTEL CORPORATION

Inventor： Jennifer Chin ,  Su Wei Lim ,  Poh Thiam Teoh ,  Ting Lok Song ,  Sun Zheng E ,  Say Cheong Gan

IPC: G06F1/32 ,  G06F3/06

Abstract: Various embodiments are generally directed to an apparatus, method and other techniques for determining when a communications port is in a first low power state, determining that a coupled device entered a low power state and enabling a second low power state based on the determination that the device has entered the low power state, the second low power state to use less power than the first low power state.