Patent search ap:("INTEL CORPORATION") AND inv:"David Harriman" Page 1

1.

发明授权
Communicating a message request transaction to a logical device 有权

公开(公告)号：US10884971B2

公开(公告)日：2021-01-05

申请号：US16518629

申请日：2019-07-22

Applicant: Intel Corporation

Inventor： David Harriman , Jasmin Ajanovic

IPC: H04J1/16 , G06F13/42 , H04L29/06 , G06F13/40 , G06F11/07

Abstract: A general input/output communication port implements a communication stack that includes a physical layer, a data link layer and a transaction layer. The transaction layer includes assembling a packet header for a message request transaction to one or more logical devices. The packet header includes a format field to indicate the length of the packet header and to further specify whether the packet header includes a data payload, a subset of a type field to indicate the packet header relates to the message request transaction and a message field. The message field includes a message to implement the message request transaction. The message includes at least one message that is selected from a group of messages. The group of messages to include a message to unlock a logical device, a message to reset a logical device, a message to indicate a correctable error condition, a message to indicate an uncorrectable error condition, a message to indicate a fatal error condition, a message to report a bad request packet, a message to indicate power management and a message to emulate an interrupt signal.

2.

发明申请
MULTIPLE UPLINK PORT DEVICES 审中-公开

公开(公告)号：US20180004703A1

公开(公告)日：2018-01-04

申请号：US15200260

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Debendra Das Sharma , Anil Vasudevan , David Harriman

IPC: G06F13/42 , G06F13/40

CPC classification number: G06F13/4282 , G06F13/4072

Abstract: A device is provided with two or more uplink ports to connect the device via two or more links to one or more sockets, where each of the sockets includes one or more processing cores, and each of the two or more links is compliant with a particular interconnect protocol. The device further includes I/O logic to identify data to be sent to the one or more processing cores for processing, determine an affinity attribute associated with the data, and determine which of the two or more links to use to send the data to the one or more processing cores based on the affinity attribute.

3.

发明授权
General input/output architecture, protocol and related methods to implement flow control 有权

公开(公告)号：US09088495B2

公开(公告)日：2015-07-21

申请号：US13730061

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Jasmin Ajanovic , David Harriman , Blaise Fanning , David Lee

IPC: G06F15/16 , H04L12/801 , G06F13/12 , G06F13/38 , G06F13/42 , G06F13/40

CPC classification number: H04L47/10 , G06F5/06 , G06F13/124 , G06F13/385 , G06F13/4059 , G06F13/42 , G06F13/4221 , G06F13/4252 , G06F13/4265 , G06F13/4269 , G06F13/4282 , H04L47/30

Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.

4.

发明授权
General input/output architecture, protocol and related methods to implement flow control 有权
Title translation: 一般输入/输出架构，协议和相关方法来实现流量控制

公开(公告)号：US09565106B2

公开(公告)日：2017-02-07

申请号：US14145384

申请日：2013-12-31

Applicant: Intel Corporation

Inventor： Jasmin Ajanovic , David Harriman , Blaise Fanning , David M. Lee

IPC: G06F15/173 , H04L12/801 , G06F13/12 , G06F13/38 , G06F13/42 , G06F13/40 , G06F5/06

CPC classification number: H04L47/10 , G06F5/06 , G06F13/124 , G06F13/385 , G06F13/4059 , G06F13/42 , G06F13/4221 , G06F13/4252 , G06F13/4265 , G06F13/4269 , G06F13/4282 , H04L47/30

Abstract: A storage device is provided to maintain a value of flow control credits allocated for a device on a channel and flow control logic is provided to receive a flow control signal over a link of an interconnect, the flow control signal indicating flow control credits allocated for the device on the channel. The flow control logic is further to update the value of flow control credits based on activity of the device on the channel.

Abstract translation: 提供存储装置以维持为信道上的设备分配的流量控制信用的值，并且提供流控制逻辑以通过互连的链路接收流控制信号，所述流控制信号指示为设备在通道上。流量控制逻辑还基于通道上的设备的活动来更新流量控制信用的值。

5.

发明申请
GENERAL INPUT/OUTPUT ARCHITECTURE, PROTOCOL AND RELATED METHODS TO IMPLEMENT FLOW CONTROL 审中-公开
Title translation: 一般输入/输出结构，协议和相关方法实施流量控制

公开(公告)号：US20150178241A1

公开(公告)日：2015-06-25

申请号：US14580073

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Jasmin Ajanovic , David Harriman , Blaise Fanning , David Lee

IPC: G06F13/42 , G06F5/06

CPC classification number: H04L47/10 , G06F5/06 , G06F13/124 , G06F13/385 , G06F13/4059 , G06F13/42 , G06F13/4221 , G06F13/4252 , G06F13/4265 , G06F13/4269 , G06F13/4282 , H04L47/30

Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.

Abstract translation: 提出了一种增强的通用输入/输出通信架构，协议和相关方法。

6.

发明授权
Multiple uplink port devices 有权

公开(公告)号：US11657015B2

公开(公告)日：2023-05-23

申请号：US17153751

申请日：2021-01-20

Applicant: Intel Corporation

Inventor： Debendra Das Sharma , Anil Vasudevan , David Harriman

IPC: G06F13/16 , G06F13/42 , G06F13/40

CPC classification number: G06F13/4282 , G06F13/4072

Abstract: A device is provided with two or more uplink ports to connect the device via two or more links to one or more sockets, where each of the sockets includes one or more processing cores, and each of the two or more links is compliant with a particular interconnect protocol. The device further includes I/O logic to identify data to be sent to the one or more processing cores for processing, determine an affinity attribute associated with the data, and determine which of the two or more links to use to send the data to the one or more processing cores based on the affinity attribute.

7.

发明授权
Two-wire link for time-multiplexed power and data transmission to multiple devices 有权

公开(公告)号：US10581545B2

公开(公告)日：2020-03-03

申请号：US15980442

申请日：2018-05-15

Applicant: Intel Corporation

Inventor： Huimin Chen , David Harriman , Yong Yang

IPC: H04J3/00 , H04J3/16 , H04W52/02 , H04Q11/04 , H04W72/04 , H04L5/14 , H04L29/08

Abstract: An apparatus is provided, where the apparatus may include a first terminal and a second terminal to be coupled to a host via a first wire and a second wire, respectively; a rechargeable storage; and a data circuitry. The apparatus may, during a first time-period, receive power via the first wire and the second wire from the host, and store the power in the rechargeable storage, and during a second time-period, transmit data from the data circuitry to the host via the first wire and the second wire. The first and second time-periods may be non-overlapping time periods. The apparatus is to refrain from transmitting any data to, or receiving any data from, the host during the first time period.

8.

发明申请
SERIAL SIDEBAND SIGNALING LINK 审中-公开

公开(公告)号：US20170235701A1

公开(公告)日：2017-08-17

申请号：US15503097

申请日：2014-12-24

Applicant: INTEL CORPORATION

Inventor： Akshay Pethe , Mahesh Wagh , David Harriman , Su Wei Lim , Debendra Das Sharma , Daniel Froelich , Venkatraman Iyer , James Jaussi , Zuoguo Wu

IPC: G06F13/42 , G06F13/38

CPC classification number: G06F13/4286 , G06F13/385 , G06F13/4027 , G06F2213/0042 , G06F2213/4002

Abstract: Techniques for embedded high speed serial interface methods are described herein. The techniques include an apparatus for sideband signaling including a first serial sideband link module and a second serial sideband link module. The first serial sideband link module is to propagate packets from an upstream port to a downstream port via a first signaling lane, and the second serial sideband link module is to propagate packets from the downstream port to the upstream port via a second signaling lane.