公开(公告)号：US10055137B2

公开(公告)日：2018-08-21

申请号：US15197617

申请日：2016-06-29

Applicant: INTEL CORPORATION

Inventor： Aliasgar S. Madraswala ,  Yogesh B. Wakchaure ,  David B. Carlton ,  Xin Guo ,  Ryan J. Norton

IPC: G06F12/02 ,  G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688

Abstract: A first type of command is suspended, by a controller of a non-volatile memory device, in response to determining that a second type of command is waiting for execution. The first type of command is split into a plurality of chunks based on a computed criteria. A second type of command is executed in between execution of at least two chunks of the first type of command.

公开(公告)号：US10095432B2

公开(公告)日：2018-10-09

申请号：US15656885

申请日：2017-07-21

Applicant: Intel Corporation

Inventor： Donia Sebastian ,  Simon D. Ramage ,  Curtis A. Gittens ,  Scott Nelson ,  David B. Carlton ,  Kai-Uwe Schmidt

IPC: G11C5/14 ,  G06F3/06

Abstract: In one embodiment, a command for a storage device may be received, wherein the command comprises a plurality of stages. Power for the plurality of stages of the command may be dynamically allocated, wherein power for a first stage of the command is allocated first, and power for each remaining stage of the command is allocated after a preceding stage is performed.

公开(公告)号：US10446238B2

公开(公告)日：2019-10-15

申请号：US15717835

申请日：2017-09-27

Applicant: Intel Corporation

Inventor： Aliasgar S. Madraswala ,  Xin Guo ,  David B. Carlton ,  Purval S. Sule

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/10

Abstract: Embodiments include apparatuses, methods, and computer devices including a multi-level NAND memory array and a memory controller coupled to the multi-level NAND memory array. The multi-level NAND memory array may include a first word line and a second word line. The memory controller may receive a first page of data and a second page of data together with a program command to program the first page of data and the second page of data into the multi-level NAND memory array. The memory controller may program the first page of data into a page of the first word line via a first pass, and further program the second page of data into a page of the second word line via a second pass, subsequent to the first pass. Other embodiments may also be described and claimed.

公开(公告)号：US09727267B1

公开(公告)日：2017-08-08

申请号：US15277524

申请日：2016-09-27

Applicant: Intel Corporation

Inventor： Donia Sebastian ,  Simon D. Ramage ,  Curtis A. Gittens ,  Scott Nelson ,  David B. Carlton ,  Kai-Uwe Schmidt

IPC: G11C5/14 ,  G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/061 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/067 ,  G06F3/0688

Abstract: In one embodiment, a command for a storage device may be received, wherein the command comprises a plurality of stages. Power for the plurality of stages of the command may be dynamically allocated, wherein power for a first stage of the command is allocated first, and power for each remaining stage of the command is allocated after a preceding stage is performed.

公开(公告)号：US10956081B2

公开(公告)日：2021-03-23

申请号：US16388761

申请日：2019-04-18

Applicant: INTEL CORPORATION

Inventor： David J. Pelster ,  David B. Carlton ,  Mark Anthony Golez ,  Xin Guo ,  Aliasgar S. Madraswala ,  Sagar S. Sidhpura ,  Sagar Upadhyay ,  Neelesh Vemula ,  Yogesh B. Wakchaure ,  Ye Zhang

IPC: G06F3/06

Abstract: A data structure is maintained for performing a program operation that is allowed to be suspended to perform reads in a NAND device, where the data structure indicates a plurality of tiers, where each tier of the plurality of tiers has a number of allowed suspends of the program operation while executing in the tier, and where a sum of the number of allowed suspends for all tiers of the plurality of tiers equals a maximum allowed number of suspends of the program operation. In response to performing a resume of the program operation, after performing a read following a suspend of the program operation, a determination is made of a tier of the plurality of tiers for the program operation and a subsequent suspend of the program operation is performed only after a measure of progress of the program operation has been exceeded in the determined tier.

公开(公告)号：US10579269B2

公开(公告)日：2020-03-03

申请号：US16105363

申请日：2018-08-20

Applicant: INTEL CORPORATION

Inventor： Aliasgar S. Madraswala ,  Yogesh B. Wakchaure ,  David B. Carlton ,  Xin Guo ,  Ryan J. Norton

IPC: G06F12/00 ,  G06F3/06

Abstract: A first type of command is suspended, by a controller of a non-volatile memory device, in response to determining that a second type of command is waiting for execution. The first type of command is split into a plurality of chunks based on a computed criteria. A second type of command is executed in between execution of at least two chunks of the first type of command.

公开(公告)号：US10521121B2

公开(公告)日：2019-12-31

申请号：US15394653

申请日：2016-12-29

Applicant: INTEL CORPORATION

Inventor： David B. Carlton ,  Xin Guo ,  Yu Du

IPC: G06F12/02 ,  G06F3/06

Abstract: Provided are an apparatus, system and method for apparatus, system and method for throttling an acceptance rate for adding host Input/Output (I/O) commands to a buffer in a non-volatile memory storage device. Information is maintained on an input rate at which I/O commands are being added to the buffer and information is maintained on an output rate at which I/O commands are processed from the buffer to apply to execute against the non-volatile memory. A determination is made of a current level of available space in the buffer and an acceptance rate at which I/O commands are added to the buffer from the host system to process based on the input rate, the output rate, the current level of available space, and an available space threshold for the buffer to maintain the buffer at the available space threshold. I/O commands are added to the buffer to process based on the acceptance rate. The I/O commands are accessed from the buffer to process to execute against the non-volatile memory.

公开(公告)号：US20180101323A1

公开(公告)日：2018-04-12

申请号：US15656885

申请日：2017-07-21

Applicant: Intel Corporation

Inventor： Donia Sebastian ,  Simon D. Ramage ,  Curtis A. Gittens ,  Scott Nelson ,  David B. Carlton ,  Kai-Uwe Schmidt

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/061 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/067 ,  G06F3/0688

Abstract: In one embodiment, a command for a storage device may be received, wherein the command comprises a plurality of stages. Power for the plurality of stages of the command may be dynamically allocated, wherein power for a first stage of the command is allocated first, and power for each remaining stage of the command is allocated after a preceding stage is performed.

公开(公告)号：US20160283111A1

公开(公告)日：2016-09-29

申请号：US14670250

申请日：2015-03-26

Applicant: Intel Corporation

Inventor： Xin Guo ,  David B. Carlton ,  Scott Nelson ,  David J. Pelster ,  Donia Sebastian

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  G06F13/1626

Abstract: Apparatus, systems, and methods to implement read operations in nonvolatile memory devices are described. In one example, a controller comprises logic to receive a first read request from a host device, place the first read request in a read queue comprising a plurality of read requests directed to the nonvolatile memory, determine a first target die and a first target plane in the nonvolatile memory for the first read request and combine the first read request with at least a second read request in the read queue to form a combined read request, wherein the second read request comprise a second target die, which is the same as the first target die, and a second target plane which is different from the first target plane. Other examples are also disclosed and claimed.

Abstract translation: 描述了在非易失性存储器件中实现读取操作的装置，系统和方法。 在一个示例中，控制器包括从主机设备接收第一读请求的逻辑，将第一读请求置于包括指向非易失性存储器的多个读请求的读队列中，确定第一目标管芯和第一目标平面 在所述非易失性存储器中用于所述第一读取请求，并将所述第一读取请求与所述读取队列中的至少第二读取请求组合以形成组合的读取请求，其中所述第二读取请求包括第二目标模具，其与 第一目标管芯和与第一靶面不同的第二靶平面。 还公开并要求保护其他实例。