公开(公告)号：US20190259713A1

公开(公告)日：2019-08-22

申请号：US16280993

申请日：2019-02-20

Applicant: INTEL CORPORATION

Inventor： ERIC J. LI ,  GUOTAO WANG ,  HUIYANG FEI ,  SAIRAM AGRAHARAM ,  OMKAR G. KARHADE ,  NITIN A. DESHPANDE

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H05K3/30 ,  H01L23/31 ,  H05K1/18 ,  H05K3/34

Abstract: Techniques for reducing warpage for microelectronic packages are provided. A warpage control layer or stiffener can be attached to a bottom surface of a substrate or layer that is used to attach the microelectronics package to a motherboard. The warpage control layer can have a thickness approximately equal to a thickness of a die of the microelectronics package. A coefficient of thermal expansion of the warpage control layer can be selected to approximately match a CTE of the die. The warpage control layer can be formed from an insulating material or a metallic material. The warpage control layer can comprise multiple materials and can include copper pillar segments to adjust the effective CTE of the warpage control layer. The warpage control layer can be positioned between the microelectronics package and the motherboard, thereby providing warpage control without contributing to the z-height of the microelectronics package.

公开(公告)号：US20210391281A1

公开(公告)日：2021-12-16

申请号：US17412840

申请日：2021-08-26

Applicant: INTEL CORPORATION

Inventor： ERIC J. LI ,  GUOTAO WANG ,  HUIYANG FEI ,  SAIRAM AGRAHARAM ,  OMKAR G. KARHADE ,  NITIN A. DESHPANDE

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H05K3/30 ,  H05K3/34 ,  H05K1/18

Abstract: Techniques for reducing warpage for microelectronic packages are provided. A warpage control layer or stiffener can be attached to a bottom surface of a substrate or layer that is used to attach the microelectronics package to a motherboard. The warpage control layer can have a thickness approximately equal to a thickness of a die of the microelectronics package. A coefficient of thermal expansion of the warpage control layer can be selected to approximately match a CTE of the die. The warpage control layer can be formed from an insulating material or a metallic material. The warpage control layer can comprise multiple materials and can include copper pillar segments to adjust the effective CTE of the warpage control layer. The warpage control layer can be positioned between the microelectronics package and the motherboard, thereby providing warpage control without contributing to the z-height of the microelectronics package.

公开(公告)号：US20180277492A1

公开(公告)日：2018-09-27

申请号：US15468067

申请日：2017-03-23

Applicant: INTEL CORPORATION

Inventor： ERIC J. LI ,  GUOTAO WANG ,  HUIYANG FEI ,  SAIRAM AGRAHARAM ,  OMKAR G. KARHADE ,  NITIN A. DESHPANDE

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H05K3/30 ,  H05K3/34 ,  H01L21/48 ,  H05K1/18

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49866 ,  H01L23/49894 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2924/3511 ,  H05K1/181 ,  H05K3/301 ,  H05K3/3436 ,  H05K2201/10378 ,  H05K2201/10734

Abstract: Techniques for reducing warpage for microelectronic packages are provided. A warpage control layer or stiffener can be attached to a bottom surface of a substrate or layer that is used to attach the microelectronics package to a motherboard. The warpage control layer can have a thickness approximately equal to a thickness of a die of the microelectronics package. A coefficient of thermal expansion of the warpage control layer can be selected to approximately match a CTE of the die. The warpage control layer can be formed from an insulating material or a metallic material. The warpage control layer can comprise multiple materials and can include copper pillar segments to adjust the effective CTE of the warpage control layer. The warpage control layer can be positioned between the microelectronics package and the motherboard, thereby providing warpage control without contributing to the z-height of the microelectronics package.