公开(公告)号：US20240311312A1

公开(公告)日：2024-09-19

申请号：US18121972

申请日：2023-03-15

Applicant: INTEL CORPORATION

Inventor： Jason BRANDT ,  Ido OUZIEL ,  Michael CHYNOWETH ,  Raoul RIVAS TOLEDANO ,  Gilbert NEIGER ,  Andreas KLEEN ,  Jacob DOWECK ,  Andrew NELSON

IPC: G06F12/1045

CPC classification number: G06F12/1045 ,  G06F2212/682

Abstract: An apparatus and method are described for reduced power TLB management. For example, one embodiment of a processor comprises: a plurality of cores; a first core of the plurality of cores comprising: a first translation lookaside buffer (TLB) to store address translations associated with page table walk operations, and power management logic to cause the first core to enter into a first low power state in which the address translations in the first TLB are no longer valid, wherein prior to entering into the low power state, the first core is to write an indication in a memory location that the first TLB no longer contains valid address translations; a second core of the plurality of cores to perform an operation requiring invalidation of one or more of the address translations previously stored in the first TLB, the second core to determine whether to transmit a request to the first core to invalidate the one or more address translations based on the indication.

公开(公告)号：US20240143513A1

公开(公告)日：2024-05-02

申请号：US17958337

申请日：2022-10-01

Applicant: Intel Corporation

Inventor： Gilbert NEIGER ,  Andreas KLEEN ,  David SHEFFIELD ,  Jason BRANDT ,  Ittai ANATI ,  Vedvyas SHANBHOGUE ,  Ido OUZIEL ,  Michael S. BAIR ,  Barry E. HUNTLEY ,  Joseph NUZMAN ,  Toby OPFERMAN ,  Michael A. ROTHMAN

IPC: G06F12/1009 ,  G06F12/0811 ,  G06F12/1027

CPC classification number: G06F12/1009 ,  G06F12/0811 ,  G06F12/1027

Abstract: An apparatus and method for switching between different types of paging using separate control registers and without disabling paging. For example, one embodiment of a processor comprises: a first control register to store a first base address of a first paging structure associated with a first type of paging having a first number of paging structure levels; a second control register to store a second base address of a second paging structure associated with a first type of paging having a second number of paging structure levels greater than the first number of paging structure levels; page walk circuitry to select either the first base address from the first control register or the second base address from the second control register responsive to a first address translation request, the selection based on a characteristic of program code initiating the address translation request.

公开(公告)号：US20240320341A1

公开(公告)日：2024-09-26

申请号：US18217361

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Andreas KLEEN ,  David SHEFFIELD ,  Xiang ZOU ,  Jason BRANDT

IPC: G06F21/57 ,  G06F9/30

CPC classification number: G06F21/575 ,  G06F9/30098

Abstract: An apparatus and method for booting a processor directly into a paged 64-bit execution environment. For example, one embodiment of an a processor comprises: a register to store a first value and a second value related to a secure boot process; a plurality of cores, at least one of which performs operations comprising: receiving a first initialization message, the core to clear a plurality of registers responsively; receiving a second initialization message and reading the first and second values responsively, the first value indicating whether a first initialization mode is supported, and the second value comprising an address pointer identifying a data structure comprising a plurality of state values; and initializing a paged 64-bit execution environment using the state values from the data structure responsive to the first value indicating the first initialization mode is supported and the data structure indicating enabling the paged 64-bit execution environment.

公开(公告)号：US20240143361A1

公开(公告)日：2024-05-02

申请号：US17958336

申请日：2022-10-01

Applicant: Intel Corporation

Inventor： Tyler SONDAG ,  Andreas KLEEN ,  David SHEFFIELD ,  Xiang ZOU ,  Terry PARKS ,  Jason BRANDT ,  Ittai ANATI

IPC: G06F9/455 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/45558 ,  G06F9/3016 ,  G06F9/3802 ,  G06F2009/45591

Abstract: An apparatus and method for implementing a new virtualized execution environment while supporting instructions and operations of a legacy virtualized execution environment. For example, one embodiment of a processor comprises: instruction processing circuitry to process instructions in accordance with a microarchitecture, the instruction processing circuitry comprising: instruction fetch circuitry to fetch the instructions; a decoder to decode the instructions; and execution circuitry to execute the instructions based on the microarchitecture; wherein the microarchitecture including hardware support for a virtual execution environment including a virtual machine monitor (VMM) and a first type of virtual machine, wherein both the VMM and the first type of virtual machine are implemented by instructions directly supported by the microarchitecture; and wherein the VMM is to support a second type of virtual machine, the second type of virtual machine including legacy instructions not fully supported by the microarchitecture, the VMM comprising a plurality of emulators, each emulator configured to emulate execution of a different type of the legacy instructions.

公开(公告)号：US20240004648A1

公开(公告)日：2024-01-04

申请号：US17856981

申请日：2022-07-02

Applicant: Intel Corporation

Inventor： Venkateswara Rao MADDURI ,  Jason BRANDT ,  Jeff WIEDEMEIER ,  Michael ESPIG

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30185 ,  G06F9/30098

Abstract: Techniques for vector unpacking are described. In some examples a single instruction is executed to perform vector unpacking. In some examples the instruction is to include one or more fields for an opcode, a destination operand identifier, a first source operand identifier, a second source operand identifier, and an immediate, wherein the opcode is to indicate execution circuitry is to interleave data elements from the identified first and second source operands according to an encoding of the immediate wherein the encoding of the immediate to include multiple controls with each control dictating what is to be written into a particular data element position of the identified destination operand;

公开(公告)号：US20190042448A1

公开(公告)日：2019-02-07

申请号：US15853640

申请日：2017-12-22

Applicant: Intel Corporation

Inventor： Raanan SADE ,  Jason BRANDT ,  Mark J. CHARNEY ,  Joseph NUZMAN ,  Leena PUTHIYEDATH ,  Rinat RAPPOPORT ,  Vivekananthan SANJEEPAN ,  Robert VALENTINE

IPC: G06F12/0877 ,  G06F12/0846 ,  G06F12/0813 ,  G06F12/0895 ,  G06F9/30

Abstract: Implementations of using tiles for caching are detailed In some implementations, an instruction execution circuitry executes one or more instructions, a register state cache coupled to the instruction execution circuitry holds thread register state in a plurality of registers, and backing storage pointer storage stores a backing storage pointer, wherein the backing storage pointer is to reference a state backing storage area in external memory to store the thread register state stored in the register state cache.

公开(公告)号：US20180276027A1

公开(公告)日：2018-09-27

申请号：US15899664

申请日：2018-02-20

Applicant: Intel Corporation

Inventor： Atul KHARE ,  Leena PUTHIYEDATH ,  Asit MALLICK ,  Jim COKE ,  Michael MISHAELI ,  Gilbert NEIGER ,  Vivekananthan SANJEEPAN ,  Jason BRANDT

IPC: G06F9/46 ,  G06F9/30

CPC classification number: G06F9/461 ,  G06F9/30003 ,  G06F9/30043 ,  G06F9/30101 ,  H05K999/99

Abstract: Embodiments of an invention related to compacted context state management are disclosed. In one embodiment, a processor includes instruction hardware and state management logic. The instruction hardware is to receive a first save instruction and a second save instruction. The state management logic is to, in response to the first save instruction, save context state in an un-compacted format in a first save area. The state management logic is also to, in response to the second save instruction, save a compaction mask and context state in a compacted format in a second save area and set a compacted-save indicator in the second save area. The state management logic is also to, in response to a single restore instruction, determine, based on the compacted-save indicator, whether to restore context from the un-compacted format in the first save area or from the compacted format in the second save area.