公开(公告)号：US20160378688A1

公开(公告)日：2016-12-29

申请号：US14752227

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： CARLOS V. ROZAS ,  MONA VIJ ,  REBEKAH M. LESLIE-HURD ,  KRYSTOF C. ZMUDZINSKI ,  SOMNATH CHAKRABARTI ,  FRANCIS X. MCKEEN ,  VINCENT R. SCARLATA ,  SIMON P. JOHNSON ,  ILYA ALEXANDROVICH ,  GILBERT NEIGER ,  VEDVYAS SHANBHOGUE ,  ITTAI ANATI

IPC: G06F12/14 ,  G06F9/30 ,  G06F21/60

CPC classification number: G06F12/1408 ,  G06F8/41 ,  G06F9/30145 ,  G06F9/45558 ,  G06F21/53 ,  G06F21/602 ,  G06F2009/4557 ,  G06F2009/45587 ,  G06F2212/1052

Abstract: A processor includes a decode unit to decode an instruction that is to indicate a page of a protected container memory, and a storage location outside of the protected container memory. An execution unit, in response to the instruction, is to ensure that there are no writable references to the page of the protected container memory while it has a write protected state. The execution unit is to encrypt a copy of the page of the protected container memory. The execution unit is to store the encrypted copy of the page to the storage location outside of the protected container memory, after it has been ensured that there are no writable references. The execution unit is to leave the page of the protected container memory in the write protected state, which is also valid and readable, after the encrypted copy has been stored to the storage location.

Abstract translation: 处理器包括解码单元，用于解码指示受保护的容器存储器的页面的指令以及受保护的容器存储器之外的存储位置。 执行单元响应于该指令，是确保在受保护的容器存储器具有写保护状态时不存在对受保护的容器存储器的页的可写引用。 执行单元是加密受保护的容器存储器的页面的副本。 在确保没有可写入引用之后，执行单元将页面的加密副本存储到受保护的容器存储器外部的存储位置。 执行单元将保护的容器存储器的页面保留在写保护状态中，该保护状态在加密的副本已被存储到存储位置之后也是有效和可读的。

公开(公告)号：US20160378684A1

公开(公告)日：2016-12-29

申请号：US14751902

申请日：2015-06-26

Applicant: INTEL CORPORATION

Inventor： KRYSTOF C. ZMUDZINSKI ,  VEDVYAS SHANBHOGUE

IPC: G06F12/10 ,  G11C7/10

CPC classification number: G06F12/1027 ,  G06F9/45558 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/1408 ,  G06F12/1441 ,  G06F12/1483 ,  G06F21/53 ,  G06F21/79 ,  G06F2009/45587 ,  G06F2212/1024 ,  G06F2212/1052 ,  G06F2212/305 ,  G06F2212/651 ,  G06F2212/657 ,  G06F2212/684

Abstract: A processor of an aspect includes at least one translation lookaside buffer (TLB) and a memory management unit (MMU). Each TLB is to store translations of logical addresses to corresponding physical addresses. The MMU, in response to a miss in the at least one TLB for a translation of a first logical address to a corresponding physical address, is to check for a multi-page protected container page versus regular page (P/R) check hint. If the multi-page P/R check hint is found, then the MMU is to check a P/R indication. If the multi-page P/R check hint is not found, then the MMU does not check the P/R indication. Other processors, methods, and systems are also disclosed.

Abstract translation: 一个方面的处理器包括至少一个翻译后备缓冲器（TLB）和存储器管理单元（MMU）。 每个TLB将逻辑地址的翻译存储到相应的物理地址。 响应于在至少一个TLB中为了将第一逻辑地址转换为对应的物理地址而错过的MMU是检查多页面受保护的容器页面与常规页面（P / R）检查提示。 如果发现多页P / R检查提示，则MMU将检查P / R指示。 如果未找到多页P / R检查提示，则MMU不会检查P / R指示。 还公开了其他处理器，方法和系统。

公开(公告)号：US20160085695A1

公开(公告)日：2016-03-24

申请号：US14495074

申请日：2014-09-24

Applicant: Intel Corporation

Inventor： REBEKAH M. LESLIE-HURD ,  FRANCIS X. MCKEEN ,  CARLOS V. ROZAS ,  KRYSTOF C. ZMUDZINSKI

IPC: G06F12/14 ,  G06F12/06

CPC classification number: G06F12/1441 ,  G06F9/52 ,  G06F21/53 ,  G06F21/74 ,  G06F21/79

Abstract: Secure memory allocation technologies are described. A processor includes a processor core and a memory controller that is coupled between the processor core and main memory. The main memory comprises a protected region including secured pages. The processor, in response to a content copy instruction, is to initialize a target page in the protected region of an application address space. The processor, in response to the content copy instruction, is also to select content of a source page in the protected region to be copied. The processor, in response to the content copy instruction, is also to copy the selected content to the target page in the protected region of the application address space.

Abstract translation: 描述了安全的内存分配技术。 处理器包括耦合在处理器核心和主存储器之间的处理器核心和存储器控制器。 主存储器包括保护区域，包括安全页面。 响应于内容复制指令的处理器是初始化应用地址空间的受保护区域中的目标页面。 处理器响应于内容复制指令，也是选择要复制的受保护区域中的源页面的内容。 响应于内容复制指令，处理器还将所选择的内容复制到应用地址空间的受保护区域中的目标页面。