公开(公告)号：US11048313B2

公开(公告)日：2021-06-29

申请号：US16369580

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Siddhartha Jana ,  Federico Ardanaz ,  Jonathan M. Eastep ,  Yaxin Shui ,  Keith Underwood

IPC: G06F1/24 ,  G06F9/00 ,  G06F1/3206 ,  G06F1/3234

Abstract: Described herein are automated hierarchical feed-back driven control mechanisms and methods, including an apparatus comprising a first circuitry, a second circuitry, and a third circuitry. The first circuitry may be operable to receive a system operating characteristic guidance. The second circuitry may be operable to provide one or more manufacturing characteristics. The third circuitry may be operable to store one or more system operating characteristics based upon the system operating characteristic guidance and the one or more manufacturing characteristics.

公开(公告)号：US11456972B2

公开(公告)日：2022-09-27

申请号：US15941381

申请日：2018-03-30

Applicant: INTEL CORPORATION

Inventor： Keith Underwood ,  Karl Brummel ,  John Greth

IPC: H04L49/901 ,  H04L45/745 ,  H04L49/35 ,  H04L67/568 ,  H04L49/9047 ,  H04L69/04

Abstract: Logic may store at least a portion of an incoming packet at a memory location in a host device in response to a communication from the host device. Logic may compare the incoming packet to a digest in an entry of a primary array. When the incoming packet matches the digest, logic may retrieve a full entry from the secondary array and compare the full entry with the first incoming packet. When the full entry matches the first incoming packet, logic may store at least a portion of the first incoming packet at the memory location. And, in the absence of a match between the first incoming packet and the digest or full entry, logic may compare the first incoming packet to subsequent entries in the primary array to identify a full entry in the secondary array that matches the first incoming packet.

公开(公告)号：US20200310515A1

公开(公告)日：2020-10-01

申请号：US16369580

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Siddhartha Jana ,  Federico Ardanaz ,  Jonathan M. Eastep ,  Yaxin Shui ,  Keith Underwood

IPC: G06F1/3206 ,  G06F1/3234

Abstract: Described herein are automated hierarchical feed-back driven control mechanisms and methods, including an apparatus comprising a first circuitry, a second circuitry, and a third circuitry. The first circuitry may be operable to receive a system operating characteristic guidance. The second circuitry may be operable to provide one or more manufacturing characteristics. The third circuitry may be operable to store one or more system operating characteristics based upon the system operating characteristic guidance and the one or more manufacturing characteristics.

公开(公告)号：US10044626B2

公开(公告)日：2018-08-07

申请号：US14757993

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Keith Underwood ,  Charles Giefer ,  Mark Debbage ,  Karl P. Brummel ,  Nathan Miller ,  Bruce Pirie

IPC: H04L12/801 ,  H04L12/807 ,  H04L12/869 ,  H04L1/16 ,  H04L1/18 ,  H04L29/06

Abstract: In an embodiment, an out-of-order, reliable, end-to-end protocol is provided that can enable direct user-level data placement and atomic operations between nodes of a multi-node network. The protocol may be optimized for low-loss environments such as High Performance Computing (HPC) applications, and may enable loss detection and de-duplication of packets through the use of a robust window state manager at a target node. A multi-node network implementing the protocol may have increased system reliability, packet throughput, and increased tolerance for adaptively routed traffic, while still allowing atomic operations to be idempotently applied directly to a user memory location.

公开(公告)号：US10200310B2

公开(公告)日：2019-02-05

申请号：US14757892

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： James Dinan ,  Mario Flajslik ,  Keith Underwood ,  David Keppel ,  Ulf Rainer Hanebutte

IPC: G06F15/167 ,  H04L12/931 ,  G06F15/173

Abstract: In an example, there is disclosed a compute node, comprising: first one or more logic elements comprising a data producer engine to produce a datum; and a host fabric interface to communicatively couple the compute node to a fabric, the host fabric interface comprising second one or more logic elements comprising a data pulling engine, the data pulling engine to: publish the datum as available; receive a pull request for the datum, the pull request comprising a node identifier for a data consumer; and send the datum to the data consumer via the fabric. There is also disclosed a method of providing a data pulling engine.

公开(公告)号：US09852107B2

公开(公告)日：2017-12-26

申请号：US14998255

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Keith Underwood ,  Charles F. Giefer ,  David Addison

IPC: G06F15/173 ,  G06F9/48 ,  G06F3/06

CPC classification number: G06F15/17331 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/067 ,  G06F9/4881 ,  G06F9/547 ,  G06F12/00 ,  G06F13/00 ,  H04L67/10

Abstract: Techniques are disclosed for algorithmic mapping of logical process identifiers in order to provide highly-scalable end-point addressing in multi-node systems capable of performing massively parallel applications. In particular, nodes initiating inter-process communication with a target process may use an initiator-side translation process that performs an algorithmic mapping to translate a logical process identifier (e.g., a rank/processing element) into a target physical node identifier and a target local process identifier. The initiating node may then use hardware fabric of a multi-node network to route the inter-process communication to an appropriate node. A node may receive an inter-process communication and may use a target-side translation process in hardware to translate the target virtual process identifier into a local process identifier for the node. The node may then execute an operation in accordance with the inter-process communication, such as a get or set against a memory associated with the node.

公开(公告)号：US20170185561A1

公开(公告)日：2017-06-29

申请号：US14757892

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： James Dinan ,  Mario Flajslik ,  Keith Underwood ,  David Keppel ,  Ulf Rainer Hanebutte

IPC: G06F15/167 ,  H04L12/931

CPC classification number: H04L49/35 ,  G06F15/17331

Abstract: In an example, there is disclosed a compute node, comprising: first one or more logic elements comprising a data producer engine to produce a datum; and a host fabric interface to communicatively couple the compute node to a fabric, the host fabric interface comprising second one or more logic elements comprising a data pulling engine, the data pulling engine to: publish the datum as available; receive a pull request for the datum, the pull request comprising a node identifier for a data consumer; and send the datum to the data consumer via the fabric. There is also disclosed a method of providing a data pulling engine.

公开(公告)号：US11150967B2

公开(公告)日：2021-10-19

申请号：US15721854

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Sayantan Sur ,  Keith Underwood ,  Ravindra Babu Ganapathi ,  Andrew Friedley

IPC: G06F9/54 ,  G06F9/30

Abstract: Methods, software, and systems for improved data transfer operations using overlapped rendezvous memory registration. Techniques are disclosed for transferring data between a first process operating as a sender and a second process operating as a receiver. The sender sends a PUT request message to the receiver including payload data stored in a send buffer and first and second match indicia. The first match indicia is used to determine whether the PUT request is expected or unexpected. If the PUT request is unexpected, an RMA GET operation is performed using the second matching indicia to pull data from the send buffer and write the data to a memory region in the user space of the process associated with the receiver. If the PUT request message is expected, the data payload with the PUT request is written to a receive buffer on the receiver determined using the first match indicia.

公开(公告)号：US20190044890A1

公开(公告)日：2019-02-07

申请号：US15941381

申请日：2018-03-30

Applicant: INTEL CORPORATION

Inventor： Keith Underwood ,  Karl Brummel ,  John Greth

IPC: H04L12/879 ,  H04L29/08

Abstract: Logic may store at least a portion of an incoming packet at a memory location in a host device in response to a communication from the host device. Logic may compare the incoming packet to a digest in an entry of a primary array. When the incoming packet matches the digest, logic may retrieve a full entry from the secondary array and compare the full entry with the first incoming packet. When the full entry matches the first incoming packet, logic may store at least a portion of the first incoming packet at the memory location. And, in the absence of a match between the first incoming packet and the digest or full entry, logic may compare the first incoming packet to subsequent entries in the primary array to identify a full entry in the secondary array that matches the first incoming packet.

公开(公告)号：US20170185563A1

公开(公告)日：2017-06-29

申请号：US14998255

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Keith Underwood ,  Charles F. Giefer ,  David Addison

IPC: G06F15/173 ,  G06F9/48 ,  G06F3/06

CPC classification number: G06F15/17331 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/067 ,  G06F9/4881 ,  G06F9/547 ,  G06F12/00 ,  G06F13/00 ,  H04L67/10

Abstract: Techniques are disclosed for algorithmic mapping of logical process identifiers in order to provide highly-scalable end-point addressing in multi-node systems capable of performing massively parallel applications. In particular, nodes initiating inter-process communication with a target process may use an initiator-side translation process that performs an algorithmic mapping to translate a logical process identifier (e.g., a rank/processing element) into a target physical node identifier and a target local process identifier. The initiating node may then use hardware fabric of a multi-node network to route the inter-process communication to an appropriate node. A node may receive an inter-process communication and may use a target-side translation process in hardware to translate the target virtual process identifier into a local process identifier for the node. The node may then execute an operation in accordance with the inter-process communication, such as a get or set against a memory associated with the node.