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    ACCELERATING FOUR-WAY PARALLEL KECCAK EXECUTION ON 256-BIT VECTOR PROCESSOR
    4.
    发明公开
    ACCELERATING FOUR-WAY PARALLEL KECCAK EXECUTION ON 256-BIT VECTOR PROCESSOR 审中-公开

    公开(公告)号：US20240211261A1

    公开(公告)日：2024-06-27

    申请号：US18145776

    申请日：2022-12-22

    Applicant: Intel Corporation

    Inventor： Santosh Ghosh ,  Christoph Dobraunig ,  Manoj Sastry

    IPC: G06F9/30

    CPC classification number: G06F9/30145 ,  G06F9/30029 ,  G06F9/30032

    Abstract: A method comprises fetching, by fetch circuitry, an encoded XOR3P instruction comprising at least one opcode, a first source identifier to identify a first register, a second source identifier to identify a second register, a third source identifier to identifier a third register, and a fourth source identifier to identify a fourth operand, wherein the first register is to store a first value, the second register is to store a second value, and the third register is to store a third value, decoding, by decode circuitry, the encoded XOR3P instruction to generate a decoded XOR3P instruction, and executing, by execution circuitry, to execute the decoded XOR3P instruction to perform a rotate operation on the third value based on the fourth operand to generate a rotated third value, perform an XOR operation on the first value, the second value, and the rotated third value to generate an XOR result, perform a rotate operation on the XOR result based on the fourth operand to generate a rotated XOR, and store the rotated XOR result.

    Voltage encoded MAC and bus scrambling
    5.
    发明授权
    Voltage encoded MAC and bus scrambling 有权

    公开(公告)号：US11949793B2

    公开(公告)日：2024-04-02

    申请号：US17868204

    申请日：2022-07-19

    Applicant: Intel Corporation

    Inventor： Marcio Juliato ,  Shabbir Ahmed ,  Christopher Gutierrez ,  Xiruo Liu ,  Manoj Sastry ,  Liuyang Yang

    IPC: H04L9/32 ,  H04L12/40

    CPC classification number: H04L9/3242 ,  H04L12/40 ,  H04L2012/40215 ,  H04L2012/40273

    Abstract: Various embodiments are generally directed to providing authentication and confidentiality mechanisms for message communication over an in-vehicle network. For example, authentication data associated with a communicating node may be transmitted over the network by encoding different predefined voltage levels on top of the message bits of the message being communicated. Different voltage levels may represent different encodings, such as a bit-pair or any bit combination of the authentication data. In a further example, messaging confidentiality between at least two communicating nodes may be achieved by pseudo-randomly flipping, or scrambling, the dominant and recessive voltages of the entire message frame at the analog level based on a pseudo-random control bit sequence.

    PROCESSOR HARDWARE AND INSTRUCTIONS FOR VECTORIZED FUSED AND-XOR
    8.
    发明公开
    PROCESSOR HARDWARE AND INSTRUCTIONS FOR VECTORIZED FUSED AND-XOR 审中-公开

    公开(公告)号：US20230305846A1

    公开(公告)日：2023-09-28

    申请号：US17703194

    申请日：2022-03-24

    Applicant: Intel Corporation

    Inventor： Andrew H. Reinders ,  Santosh Ghosh ,  Manoj Sastry

    IPC: G06F9/30 ,  G06F9/38

    CPC classification number: G06F9/30145 ,  G06F9/30036 ,  G06F9/30029 ,  G06F9/3001 ,  G06F9/3802

    Abstract: A method comprises fetching, by fetch circuitry, an encoded vectorized AND-XOR instruction comprising an opcode, a first source identifier, a second source identifier, a third source identifier, and a destination identifier, decoding, by decode circuitry, the decoded vectorized AND-XOR instruction to generate a decoded vectorized AND-XOR instruction, and executing, by execution circuitry, the decoded vectorized AND-XOR instruction to retrieve operands representing a product coefficient at an index position from the first source, a coefficient of a first polynomial from the second source, and a coefficient of a second polynomial from the third source, perform, in an atomic fashion, a vectorized AND-XOR operation to generate updated value of the product coefficient, and store the product coefficient of the output polynomial in a register file accessible to the execution circuitry.

    Post-quantum secure remote attestation for autonomous systems
    10.
    发明授权
    Post-quantum secure remote attestation for autonomous systems 有权

    公开(公告)号：US11575515B2

    公开(公告)日：2023-02-07

    申请号：US17133558

    申请日：2020-12-23

    Applicant: Intel Corporation

    Inventor： Santosh Ghosh ,  Marcio Juliato ,  Manoj Sastry

    IPC: H04L29/06 ,  H04L9/32 ,  H04L9/08 ,  G06F8/71

    Abstract: A method comprises maintaining, for at least one remote device, a security footprint and a verified version of a software stack for the remote device, generating an attestation initiation token that includes a nonce to be used to generate an XMSS signature for attestation of the remote device, sending the attestation initiation token to the remote device, receiving, from the remote device, a modified message representative including a hash of a current version of a software stack for the remote device and an indicator of a version number of the current version of the software stack for the remote device, validating the hash, and in response to a determination that the hash is valid, generating an XMSS signature using the security footprint and the current version of a software stack for the remote device and a security footprint for the apparatus.

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