公开(公告)号：US10372620B2

公开(公告)日：2019-08-06

申请号：US15395259

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Poovaiah M. Palangappa

IPC: G06F3/06 ,  G06F12/1018

Abstract: Apparatuses, systems, and methods for deduplicating data using small data segments are described. Data strings are divided into a plurality of data segments having an original sequence order, and the data segments are rearranged according to an ordered sequence. The original sequence order of each data string is written to memory with a pointer to the ordered sequence of the data segments.

公开(公告)号：US20170186500A1

公开(公告)日：2017-06-29

申请号：US14998240

申请日：2015-12-23

Applicant: INTEL CORPORATION

Inventor： Ravi H. Motwani ,  Zion S. Kwok ,  Poovaiah M. Palangappa

IPC: G11C29/44 ,  G06F11/16 ,  G06F11/25 ,  G11C16/26 ,  H03M13/29

CPC classification number: G06F11/1612 ,  G11C16/26 ,  G11C29/12 ,  G11C29/42 ,  G11C29/4401 ,  H03M13/05 ,  H03M13/1102 ,  H03M13/19 ,  H03M13/23 ,  H03M13/2906 ,  H03M13/2909 ,  H03M13/2918 ,  H03M13/2957

Abstract: Memory circuit defect correction in accordance with one aspect of the present description, logically divides a block of data bits into a plurality of data bit sections, each data bit section to be written into and stored in an associated memory section of a block of memory logically divided into a plurality memory sections. In one embodiment, for each data bit section and its associated memory section, the logical values of all the user data bits of the data bit section are selectively flipped so that the logical value of a user data bit to be written into a defective bitcell, matches the fixed read output of a defective bit cell. A bitcell in each memory section may be utilized to set a flip-flag to indicate whether or not the data bits of the memory section have been flipped. Other aspects are described herein.

公开(公告)号：US12126361B2

公开(公告)日：2024-10-22

申请号：US17700022

申请日：2022-03-21

Applicant: Intel Corporation

Inventor： Poovaiah M. Palangappa ,  Zion S. Kwok ,  Ravi H. Motwani

IPC: H03M13/00 ,  G06F3/06 ,  H03M13/11 ,  H03M13/15

CPC classification number: H03M13/159 ,  G06F3/0619 ,  G06F3/0644 ,  G06F3/0659 ,  G06F3/0679 ,  H03M13/1105 ,  H03M13/1177

Abstract: A memory controller system includes error correction circuitry and erasure decoder circuitry. A retry flow is triggered when the memory controller's error checking and correction (ECC) detects an uncorrectable codeword. Error correction circuitry generates erasure codewords from the codeword with uncorrectable errors. The memory controller computes the syndrome weight of the erasure codewords. For example, the erasure decoder circuitry receives the erasure codewords and computes the syndrome weights. Error correction circuitry orders the erasure codewords based on their corresponding syndrome weights. Then error correction circuitry selects a subset of the codewords, and sends them to erasure decoder circuitry. Erasure decoder circuitry receives the selected codewords and decodes them.

公开(公告)号：US11146289B2

公开(公告)日：2021-10-12

申请号：US16370178

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Aman Bhatia ,  Zion S. Kwok ,  Justin Kang ,  Poovaiah M. Palangappa ,  Santhosh K. Vanaparthy

IPC: H03M13/11 ,  G11C29/52 ,  G06F11/10 ,  G11C29/04

Abstract: Examples include techniques to use intrinsic information when implementing a bit-flipping algorithm. An error correction control (ECC) decoder uses the intrinsic information to decode a low density parity count (LDPC) codeword. The intrinsic information including bits of a copy of a received LDPC codeword are compared to bits for variable nodes during an iteration of the bit-flipping algorithm to aid a determination as whether one or more bits for the variable nodes are to be flipped.

公开(公告)号：US11088707B2

公开(公告)日：2021-08-10

申请号：US16458021

申请日：2019-06-29

Applicant: Intel Corporation

Inventor： Poovaiah M. Palangappa ,  Zion S. Kwok

IPC: H03M13/11 ,  G06F17/16

Abstract: A low-density parity-check (LDPC) decoder has a check node storage (CNS) architecture to reduce the gate count for the decoder implementation, resulting in a lower footprint relative to traditional designs. The CNS architecture allows a controller to selectively, dynamically swap check nodes of the LDPC decoder between latching circuitry and a volatile memory. The controller can to store active check nodes in the latching circuitry and check nodes not active for a computation in the volatile memory.

公开(公告)号：US11063607B2

公开(公告)日：2021-07-13

申请号：US16422891

申请日：2019-05-24

Applicant: INTEL CORPORATION

Inventor： Poovaiah M. Palangappa ,  Zion S. Kwok

IPC: H03M13/11 ,  H03M7/30 ,  H03M13/37 ,  H03M13/00

Abstract: Provided are an apparatus, storage device, and method for compressing error vectors for decoding logic to store compressed in an decoder memory used by the decoding logic. A decoder decodes codewords to produce error vectors used to decode the codewords. A decoder memory device stores the error vectors. A compression unit receives the error vector from the decoder during decoding of the codeword. Each bit in the error vector has one of a first value and a second value. A determination is made of at least one bit location in the error vector having the first value. At least one pointer is stored in a row of memory cells in the decoder memory device indicating the determined at least one bit location in the codeword having the first value.

公开(公告)号：US20180188971A1

公开(公告)日：2018-07-05

申请号：US15395259

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Poovaiah M. Palangappa

IPC: G06F3/06 ,  G06F12/1018

CPC classification number: G06F12/1018 ,  G06F3/0608 ,  G06F3/0641 ,  G06F3/0679 ,  G06F3/0688

Abstract: Apparatuses, systems, and methods for deduplicating data using small data segments are described. Data strings are divided into a plurality of data segments having an original sequence order, and the data segments are rearranged according to an ordered sequence. The original sequence order of each data string is written to memory with a pointer to the ordered sequence of the data segments.