公开(公告)号：US11088707B2

公开(公告)日：2021-08-10

申请号：US16458021

申请日：2019-06-29

Applicant: Intel Corporation

Inventor： Poovaiah M. Palangappa ,  Zion S. Kwok

IPC: H03M13/11 ,  G06F17/16

Abstract: A low-density parity-check (LDPC) decoder has a check node storage (CNS) architecture to reduce the gate count for the decoder implementation, resulting in a lower footprint relative to traditional designs. The CNS architecture allows a controller to selectively, dynamically swap check nodes of the LDPC decoder between latching circuitry and a volatile memory. The controller can to store active check nodes in the latching circuitry and check nodes not active for a computation in the volatile memory.

公开(公告)号：US11063607B2

公开(公告)日：2021-07-13

申请号：US16422891

申请日：2019-05-24

Applicant: INTEL CORPORATION

Inventor： Poovaiah M. Palangappa ,  Zion S. Kwok

IPC: H03M13/11 ,  H03M7/30 ,  H03M13/37 ,  H03M13/00

Abstract: Provided are an apparatus, storage device, and method for compressing error vectors for decoding logic to store compressed in an decoder memory used by the decoding logic. A decoder decodes codewords to produce error vectors used to decode the codewords. A decoder memory device stores the error vectors. A compression unit receives the error vector from the decoder during decoding of the codeword. Each bit in the error vector has one of a first value and a second value. A determination is made of at least one bit location in the error vector having the first value. At least one pointer is stored in a row of memory cells in the decoder memory device indicating the determined at least one bit location in the codeword having the first value.

公开(公告)号：US20200019348A1

公开(公告)日：2020-01-16

申请号：US16586428

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Rajesh Sundaram ,  Zion S. Kwok ,  Muthukumar Swaminathan

IPC: G06F3/06

Abstract: Embodiments are directed towards apparatuses, methods, and systems including a pre-read command to eliminate an additional access of read data from a storage location of a memory device. In embodiments, a memory controller issues a pre-read command to store read data in a pre-read latch. In embodiments, the command is issued during a first access of the read data from a storage location in connection with a modify-write operation of the read data. In embodiments, the pre-read latch is located in or coupled to a selected partition of a memory device that includes the storage location that stores the read data. In embodiments, the memory controller subsequently issues a modify-write command to compare the read data stored in the pre-read latch with incoming data, to eliminate a need for a second access of the storage location during completion of the modify-write operation. Additional embodiments may be described and claimed.

公开(公告)号：US20200012554A1

公开(公告)日：2020-01-09

申请号：US16578039

申请日：2019-09-20

Applicant: Intel Corporation

Inventor： Ravi H. Motwani ,  Zion S. Kwok

IPC: G06F11/10 ,  G06F7/58 ,  G06F7/76 ,  H03M13/11

Abstract: Embodiments described include methods, apparatuses, and systems including a permutation generator to permute locations of one or more bits (e.g., data bits and/or parity bits) in a codeword. In embodiments, the bits are to be written to a memory device based on the permuted locations to reduce a recurrence of bit error patterns associated with the bits when stored in the memory device. In some embodiments, the locations are based at least in part on a pseudorandom number, generated based at least in part on information available at a read time and a write time. In some embodiments, the pseudorandom number is based upon a memory address of the memory device, such as a 3D NAND or other memory device. Additional embodiments may be described and claimed.

公开(公告)号：US10481974B2

公开(公告)日：2019-11-19

申请号：US15636635

申请日：2017-06-28

Applicant: INTEL CORPORATION

Inventor： Zion S. Kwok ,  Santhosh K. Vanaparthy ,  Ravi H. Motwani

IPC: G06F11/00 ,  G06F11/10 ,  G11C16/34 ,  G11C11/56 ,  G11C16/10

Abstract: Provided are an apparatus, non-volatile memory storage device and method for detecting drift in in non-volatile memory. A determination is made as to whether bits to write have more of a first value than a second value. Each of the bits are flipped to another of the first or second value when the bits have more of the first value than the second value. Indication is made whether the bits were flipped or not flipped. Parity is calculated for the bits and the bits and the parity for the bits are written to a location in the non-volatile memory. The bits at the location in the non-volatile memory are read and each of the bits having the first value are flipped to the second value and each of the bits having the second value are flipped to the first value in response to indication that the bits were flipped.

公开(公告)号：US20180286469A1

公开(公告)日：2018-10-04

申请号：US15474659

申请日：2017-03-30

Applicant: INTEL CORPORATION

Inventor： Zion S. Kwok

IPC: G11C7/22

CPC classification number: G11C7/22 ,  G06F13/1668 ,  G11C16/26 ,  G11C29/023 ,  G11C29/12015 ,  G11C29/40 ,  G11C29/50012

Abstract: A memory controller circuitry includes a timestamp circuitry and a demarcation voltage (VDM) selection circuitry. The timestamp circuitry is to capture a global timer index from a global timer having a granularity, G. The timestamp circuitry is further to fetch a timestamp for a memory block that includes a group of sub-blocks that includes a target sub-block. The demarcation voltage (VDM) selection circuitry is to fetch a combined count from a count store. The combined count represents a combined state. The combined state includes a target individual state of the target sub-block and a respective individual state of each of at least one other sub-block of the group of sub-blocks included in the memory block.

公开(公告)号：US09619324B2

公开(公告)日：2017-04-11

申请号：US14126310

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Zion S. Kwok ,  Ravi H. Motwani ,  Kiran Pangal ,  Prashant S. Damle

IPC: G06F11/10 ,  G06F12/00 ,  G11C29/52 ,  H03M13/15

CPC classification number: G06F11/1068 ,  G06F11/10 ,  G06F11/1044 ,  G06F11/108 ,  G06F12/00 ,  G06F2212/7207 ,  G11C29/52 ,  H03M13/1515 ,  H03M13/152

Abstract: Apparatus, systems, and methods for error correction in memory are described. In one embodiment, a memory controller comprises logic to receive a read request for data stored in a memory, retrieve the data and at least one associated error correction codeword, wherein the data and an associated error correction codeword is distributed across a plurality of memory devices in memory, apply a first error correction routine to decode the error correction codeword retrieved with the data and in response to an uncorrectable error in the error correction codeword, apply a second error correction routine to the plurality of devices in memory. Other embodiments are also disclosed and claimed.

公开(公告)号：US12230346B2

公开(公告)日：2025-02-18

申请号：US17358421

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Hemant P. Rao ,  Raymond W. Zeng ,  Prashant S. Damle ,  Zion S. Kwok ,  Kiran Pangal ,  Mase J. Taub

IPC: G11C29/00 ,  G11C7/06 ,  G11C29/12 ,  G11C29/42 ,  G11C29/44 ,  G11C29/50

Abstract: A read technique for both SLC (single level cell) and MLC (multi-level cell) cross-point memory can mitigate drift-related errors with minimal or no drift tracking. In one example, a read at a higher magnitude voltage is applied first, which causes the drift for cells in a lower threshold voltage state to be reset. In one example, the read at the first voltage can be a full float read to minimize disturb. A second read can then be performed at a lower voltage without the need to adjust the read voltage due to drift.

公开(公告)号：US12126361B2

公开(公告)日：2024-10-22

申请号：US17700022

申请日：2022-03-21

Applicant: Intel Corporation

Inventor： Poovaiah M. Palangappa ,  Zion S. Kwok ,  Ravi H. Motwani

IPC: H03M13/00 ,  G06F3/06 ,  H03M13/11 ,  H03M13/15

CPC classification number: H03M13/159 ,  G06F3/0619 ,  G06F3/0644 ,  G06F3/0659 ,  G06F3/0679 ,  H03M13/1105 ,  H03M13/1177

Abstract: A memory controller system includes error correction circuitry and erasure decoder circuitry. A retry flow is triggered when the memory controller's error checking and correction (ECC) detects an uncorrectable codeword. Error correction circuitry generates erasure codewords from the codeword with uncorrectable errors. The memory controller computes the syndrome weight of the erasure codewords. For example, the erasure decoder circuitry receives the erasure codewords and computes the syndrome weights. Error correction circuitry orders the erasure codewords based on their corresponding syndrome weights. Then error correction circuitry selects a subset of the codewords, and sends them to erasure decoder circuitry. Erasure decoder circuitry receives the selected codewords and decodes them.

公开(公告)号：US11146289B2

公开(公告)日：2021-10-12

申请号：US16370178

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Aman Bhatia ,  Zion S. Kwok ,  Justin Kang ,  Poovaiah M. Palangappa ,  Santhosh K. Vanaparthy

IPC: H03M13/11 ,  G11C29/52 ,  G06F11/10 ,  G11C29/04

Abstract: Examples include techniques to use intrinsic information when implementing a bit-flipping algorithm. An error correction control (ECC) decoder uses the intrinsic information to decode a low density parity count (LDPC) codeword. The intrinsic information including bits of a copy of a received LDPC codeword are compared to bits for variable nodes during an iteration of the bit-flipping algorithm to aid a determination as whether one or more bits for the variable nodes are to be flipped.