公开(公告)号：US20160225665A1

公开(公告)日：2016-08-04

申请号：US15096609

申请日：2016-04-12

Applicant: Intel Corporation

Inventor： HUI JAE YOO ,  TEJASWI K. INDUKURI ,  RAMANAN V. CHEBIAM ,  JAMES S. CLARKE

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76849 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76882 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53242 ,  H01L23/53252 ,  H01L23/53257 ,  H01L23/53266 ,  H01L2224/45015 ,  H01L2924/0002 ,  H01L2924/00011 ,  H01L2924/00

Abstract: A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ρ1 and the core material exhibits a second resistivity ρ2 and ρ2 is less than ρ1.

Abstract translation: 介电层及其形成方法。 限定在电介质层中的开口和沉积在开口内的电线，其中电线包括由护套材料围绕的芯材料，其中护套材料表现出第一电阻率ρ1，并且芯材料表现出第二电阻率ρ2且ρ2较小 比ρ1。

公开(公告)号：US20210020502A1

公开(公告)日：2021-01-21

申请号：US17061062

申请日：2020-10-01

Applicant: Intel Corporation

Inventor： HUI JAE YOO ,  TEJASWI K. INDUKURI ,  RAMANAN V. CHEBIAM ,  JAMES S. CLARKE

IPC: H01L21/768 ,  H01L23/532

Abstract: A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ρ1 and the core material exhibits a second resistivity ρ2 and ρ2 is less than ρ1.

公开(公告)号：US20170372950A1

公开(公告)日：2017-12-28

申请号：US15631701

申请日：2017-06-23

Applicant: Intel Corporation

Inventor： HUI JAE YOO ,  TEJASWI K. INDUKURI ,  RAMANAN V. CHEBIAM ,  JAMES S. CLARKE

IPC: H01L21/768 ,  H01L23/532

Abstract: A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ρ1 and the core material exhibits a second resistivity ρ2 and ρ2 is less than ρ1.

公开(公告)号：US20160005692A1

公开(公告)日：2016-01-07

申请号：US14855792

申请日：2015-09-16

Applicant: INTEL CORPORATION

Inventor： MANISH CHANDHOK ,  HUI JAE YOO ,  CHRISTOPHER J. JEZEWSKI ,  RAMANAN V. CHEBIAM ,  COLIN T. CARVER

IPC: H01L23/532

CPC classification number: H01L23/53238 ,  H01L21/7682 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/5222 ,  H01L23/5283 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A metallization layer including a fully clad interconnect and a method of forming a fully clad interconnect. An opening is formed in a dielectric layer, wherein the dielectric layer has a surface and the opening includes walls and a bottom. A diffusion barrier layer and an adhesion layer are deposited on the dielectric layer. An interconnect material is deposited on the dielectric layer and reflowed into the opening forming an interconnect. An adhesion capping layer and diffusion barrier capping layer are deposited over the interconnect. The interconnect is surrounded by the adhesion layer and the adhesion capping layer and the adhesion layer and the adhesion capping layer are surrounded by the diffusion barrier layer and the diffusion capping layer.