公开(公告)号：US20170263551A1

公开(公告)日：2017-09-14

申请号：US15529483

申请日：2014-12-24

Applicant: INTEL CORPORATION

Inventor： ROBERT L. BRISTOL ,  MANISH CHANDHOK ,  JASMEET S. CHAWLA ,  FLORIAN GSTREIN ,  EUNGNAK HAN ,  RAMI HOURANI ,  KEVIN LIN ,  RICHARD E. SCHENKER ,  TODD R. YOUNKIN

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76897 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2221/1026

Abstract: Embodiments of the invention include an interconnect structure and methods of forming such structures. In an embodiment, the interconnect structure may include an interlayer dielectric (ILD) with a first hardmask layer over a top surface of the ILD. Certain embodiments include one or more first interconnect lines in the ILD and a first dielectric cap positioned above each of the first interconnect lines. For example a surface of the first dielectric cap may contact a top surface of the first hardmask layer. Embodiments may also include one or more second interconnect lines in the ILD arranged in an alternating pattern with the first inter-connect lines. In an embodiment, a second dielectric cap is formed over a top surface of each of the second interconnect lines. For example, a surface of the second dielectric cap contacts a top surface of the first hardmask layer.

公开(公告)号：US20170263553A1

公开(公告)日：2017-09-14

申请号：US15529484

申请日：2014-12-24

Applicant: INTEL CORPORATION

Inventor： RICHARD E. SCHENKER ,  MANISH CHANDHOK ,  ROBERT L. BRISTOL ,  MAURO J. KOBRINSKY ,  KEVIN LIN

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/5283 ,  H01L23/53295

Abstract: Embodiments of the invention include interconnect structures with overhead vias and through vias that are self-aligned with interconnect lines and methods of forming such structures. In an embodiment, an interconnect structure is formed in an interlayer dielectric (ILD). One or more first interconnect lines may be formed in the ILD. The interconnect structure may also include one or more second interconnect lines in the ILD that arranged in an alternating pattern with the first interconnect lines. Top surfaces of each of the first and second interconnect lines may be recessed below a top surface of the ILD. The interconnect structure may include a self-aligned overhead via formed over one or more of the first interconnect lines or over one or more of the second interconnect lines. In an embodiment, a top surface of the self-aligned overhead via is substantially coplanar with a top surface of the ILD.

公开(公告)号：US20160005692A1

公开(公告)日：2016-01-07

申请号：US14855792

申请日：2015-09-16

Applicant: INTEL CORPORATION

Inventor： MANISH CHANDHOK ,  HUI JAE YOO ,  CHRISTOPHER J. JEZEWSKI ,  RAMANAN V. CHEBIAM ,  COLIN T. CARVER

IPC: H01L23/532

CPC classification number: H01L23/53238 ,  H01L21/7682 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/5222 ,  H01L23/5283 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A metallization layer including a fully clad interconnect and a method of forming a fully clad interconnect. An opening is formed in a dielectric layer, wherein the dielectric layer has a surface and the opening includes walls and a bottom. A diffusion barrier layer and an adhesion layer are deposited on the dielectric layer. An interconnect material is deposited on the dielectric layer and reflowed into the opening forming an interconnect. An adhesion capping layer and diffusion barrier capping layer are deposited over the interconnect. The interconnect is surrounded by the adhesion layer and the adhesion capping layer and the adhesion layer and the adhesion capping layer are surrounded by the diffusion barrier layer and the diffusion capping layer.