公开(公告)号：US20160343665A1

公开(公告)日：2016-11-24

申请号：US15225392

申请日：2016-08-01

Applicant: INTEL CORPORATION

Inventor： CHRISTOPHER J. JEZEWSKI ,  DAVID J. MICHALAK ,  KANWAL JIT SINGH ,  ALAN M. MYERS

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/311 ,  H01L23/528

CPC classification number: H01L23/5329 ,  H01L21/02203 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/7682 ,  H01L21/76822 ,  H01L21/76826 ,  H01L21/76838 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Techniques are disclosed for forming interconnects in porous dielectric materials. In accordance with some embodiments, the porosity of a host dielectric layer may be reduced temporarily by stuffing its pores with a sacrificial pore-stuffing material, such as titanium nitride (TiN), titanium dioxide (TiO2), or other suitable sacrificial material having a high etch selectivity compared to the metallization and dielectric material of the interconnect. After interconnect formation within the stuffed dielectric layer, the sacrificial pore-stuffing material can be removed from the pores of the host dielectric. In some cases, removal and curing can be performed with minimal or otherwise negligible effect on the dielectric constant (κ-value), leakage performance, and/or time-dependent dielectric breakdown (TDDB) properties of the host dielectric layer. Some embodiments can be utilized, for example, in processes involving atomic layer deposition (ALD)-based and/or chemical vapor deposition (CVD)-based backend metallization of highly porous, ultra-low-κ (ULK) dielectric materials.

Abstract translation: 公开了用于在多孔电介质材料中形成互连的技术。 根据一些实施例，可以通过用诸如氮化钛（TiN），二氧化钛（TiO 2）或其它合适的牺牲材料的牺牲孔填充材料填充其孔来临时减小主介质层的孔隙率， 与互连的金属化和介电材料相比，具有高蚀刻选择性。 在填充电介质层内形成互连之后，可以从主电介质的孔中去除牺牲孔填充材料。 在某些情况下，可以对主介电层的介电常数（κ值），泄漏性能和/或时间依赖的介电击穿（TDDB）性能产生最小或其他可忽略的影响来进行去除和固化。 一些实施例可以用于例如涉及基于原子层沉积（ALD）的和/或化学气相沉积（CVD）的高多孔，超低κ（ULK）电介质材料的后端金属化的工艺。

公开(公告)号：US20160005692A1

公开(公告)日：2016-01-07

申请号：US14855792

申请日：2015-09-16

Applicant: INTEL CORPORATION

Inventor： MANISH CHANDHOK ,  HUI JAE YOO ,  CHRISTOPHER J. JEZEWSKI ,  RAMANAN V. CHEBIAM ,  COLIN T. CARVER

IPC: H01L23/532

CPC classification number: H01L23/53238 ,  H01L21/7682 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/5222 ,  H01L23/5283 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A metallization layer including a fully clad interconnect and a method of forming a fully clad interconnect. An opening is formed in a dielectric layer, wherein the dielectric layer has a surface and the opening includes walls and a bottom. A diffusion barrier layer and an adhesion layer are deposited on the dielectric layer. An interconnect material is deposited on the dielectric layer and reflowed into the opening forming an interconnect. An adhesion capping layer and diffusion barrier capping layer are deposited over the interconnect. The interconnect is surrounded by the adhesion layer and the adhesion capping layer and the adhesion layer and the adhesion capping layer are surrounded by the diffusion barrier layer and the diffusion capping layer.

公开(公告)号：US20160268218A1

公开(公告)日：2016-09-15

申请号：US15155791

申请日：2016-05-16

Applicant: INTEL CORPORATION

Inventor： CHRISTOPHER J. JEZEWSKI ,  MAURO J. KOBRINSKY ,  DANIEL PANTUSO ,  SIDDHARTH B. BHINGARDE ,  MICHAEL P. O'DAY

IPC: H01L23/00 ,  H01L23/532 ,  H01L23/48 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L23/562 ,  H01L23/293 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/535 ,  H01L23/5381 ,  H01L23/5386 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Techniques and structure are disclosed for enhancing fracture resistance of back-end interconnects and other such interconnect structures by increasing via density. Increased via density can be provided, for example, within the filler/dummified portion(s) of adjacent circuit layers within a die. In some cases, an electrically isolated (floating) filler line of an upper circuit layer may include a via which lands on a floating filler line of a lower circuit layer in a region corresponding to where the filler lines cross/intersect. In some such cases, the floating filler line of the upper circuit layer may be formed as a dual-damascene structure including such a via. In some embodiments, a via similarly may be provided between a floating filler line of the upper circuit layer and a sufficiently electrically isolated interconnect line of the lower circuit layer. The techniques/structure can be used to provide mechanical integrity for the die.

Abstract translation: 公开了通过增加通孔密度来提高后端互连和其它这种互连结构的抗断裂性的技术和结构。 可以例如在模具内的相邻电路层的填充/加工部分内提供通孔密度的增加。 在一些情况下，上电路层的电隔离（浮置）填充线可以包括在对应于填充线交叉/相交的区域中的下电路层的浮动填充线上的通孔。 在一些这样的情况下，上电路层的浮动填充线可以形成为包括这种通孔的双镶嵌结构。 在一些实施例中，可以在上电路层的浮动填充线和下电路层的充分电隔离的互连线之间提供通孔。 技术/结构可用于为模具提供机械完整性。