公开(公告)号：US20190004916A1

公开(公告)日：2019-01-03

申请号：US16026870

申请日：2018-07-03

Applicant: Intel Corporation

Inventor： Raul Martinez ,  Enric Gibert Codina ,  Pedro Lopez ,  Marti Torrents Lapuerta ,  Polychronis Xekalakis ,  Georgios Tournavitis ,  Kyriakos A. Stavrou ,  Demos Pavlou ,  Daniel Ortega ,  Alejandro Martinez Vicente ,  Pedro Marcuello ,  Grigorios Magklis ,  Josep M. Codina ,  Crispin Gomez Requena ,  Antonio Gonzalez ,  Mirem Hyuseinova ,  Christos Kotselidis ,  Fernando Latorre ,  Marc Lupon ,  Carlos Madriles

IPC: G06F11/30 ,  G06F12/0862 ,  G06F11/34

Abstract: A combination of hardware and software collect profile data for asynchronous events, at code region granularity. An exemplary embodiment is directed to collecting metrics for prefetching events, which are asynchronous in nature. Instructions that belong to a code region are identified using one of several alternative techniques, causing a profile bit to be set for the instruction, as a marker. Each line of a data block that is prefetched is similarly marked. Events corresponding to the profile data being collected and resulting from instructions within the code region are then identified. Each time that one of the different types of events is identified, a corresponding counter is incremented. Following execution of the instructions within the code region, the profile data accumulated in the counters are collected, and the counters are reset for use with a new code region.

公开(公告)号：US09389871B2

公开(公告)日：2016-07-12

申请号：US13840363

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Marc Lupon ,  Grigorios Magklis ,  Sridhar Samudrala ,  Raul Martinez ,  Kyriakos A. Stavrou ,  Enric Gibert Codina

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/455

CPC classification number: G06F9/3861 ,  G06F9/3001 ,  G06F9/3017 ,  G06F9/45508

Abstract: An error handling method includes identifying a code region eligible for cumulative multiply add (CMA) optimization and translating code region instructions into interpreter code instructions, which may include translating sequences of multiply add instructions in the code region instructions into fusion code including CMA instructions. Floating point (FP) exceptions generated by the fusion code may be monitored and at least a portion of the code region instructions may be re-translated to eliminate some or all fusion code if CMA intermediate rounding exceptions exceed a threshold.

Abstract translation: 错误处理方法包括识别符合累积乘法（CMA）优化的代码区域并将代码区域指令转换为解释器代码指令，其可以包括将代码区域指令中的乘法加法指令的序列转换成包括CMA指令的融合代码。 可以监视由融合码产生的浮点（FP）异常，并且如果CMA中间舍入异常超过阈值，则可以重新转换码区指令的至少一部分以消除一些或全部融合码。

公开(公告)号：US09823925B2

公开(公告)日：2017-11-21

申请号：US14229179

申请日：2014-03-28

Applicant: Intel Corporation

Inventor： Denis M. Khartikov ,  Rupert Brauch ,  Raul Martinez ,  Naveen Neelakantam ,  Thang Vu

IPC: G06F9/00 ,  G06F9/44 ,  G06F9/30

CPC classification number: G06F9/30032 ,  G06F9/30036 ,  G06F9/3017 ,  G06F9/384 ,  G06F9/3855

Abstract: A processor includes allocation unit with logic to receive a logical move instruction. The logical move instruction includes a source logical register as a source parameter and a destination logical register as a destination parameter. The source logical register is assigned to a source physical register and the destination logical register is assigned to a destination physical register. The allocation unit includes logic to assign a first value of the source logical register to the destination logical register and to maintain a second value of the destination physical register before and after the assignment of the first value to the destination logical register.

公开(公告)号：US10157063B2

公开(公告)日：2018-12-18

申请号：US13631402

申请日：2012-09-28

Applicant: INTEL CORPORATION

Inventor： Polychronis Xekalakis ,  Pedro Marcuello ,  Alejandro Vicente Martinez ,  Christos E. Kotselidis ,  Grigorios Magklis ,  Fernando Latorre ,  Raul Martinez ,  Josep M. Codina ,  Enric Gibert Codina ,  Crispin Gomez Requena ,  Antonio Gonzelez ,  Mirem Hyuseinova ,  Pedro Lopez ,  Marc Lupon ,  Carlos Madriles ,  Daniel Ortega ,  Demos Pavlou ,  Kyriakos A. Stavrou ,  Georgios Tournavitis

IPC: G06F9/38 ,  G06F9/30

Abstract: A computer-readable storage medium, method and system for optimization-level aware branch prediction is described. A gear level is assigned to a set of application instructions that have been optimized. The gear level is also stored in a register of a branch prediction unit of a processor. Branch prediction is then performed by the processor based upon the gear level.

公开(公告)号：US20140281419A1

公开(公告)日：2014-09-18

申请号：US13840363

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Marc Lupon ,  Grigorios Magklis ,  Sridhar Samudrala ,  Raul Martinez ,  Kyriakos A. Stavrou ,  Enric Gibert Codina

IPC: G06F9/38

CPC classification number: G06F9/3861 ,  G06F9/3001 ,  G06F9/3017 ,  G06F9/45508

Abstract: An error handling method includes identifying a code region eligible for cumulative multiply add (CMA) optimization and translating code region instructions into interpreter code instructions, which may include translating sequences of multiply add instructions in the code region instructions into fusion code including CMA instructions. Floating point (FP) exceptions generated by the fusion code may be monitored and at least a portion of the code region instructions may be re-translated to eliminate some or all fusion code if CMA intermediate rounding exceptions exceed a threshold.

Abstract translation: 错误处理方法包括识别符合累积乘法（CMA）优化的代码区域并将代码区域指令转换为解释器代码指令，其可以包括将代码区域指令中的乘法加法指令的序列转换成包括CMA指令的融合代码。 可以监视由融合码产生的浮点（FP）异常，并且如果CMA中间舍入异常超过阈值，则可以重新转换码区指令的至少一部分以消除一些或全部融合码。