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公开(公告)号：US20210082481A1
公开(公告)日：2021-03-18
申请号：US17107704
申请日：2020-11-30
Applicant: Intel Corporation
Inventor： Navindra Navaratnam , Nasser A. Kurd , Bee Min Teng , Raymond Chong , Nasirul I. Chowdhury , Ali M. El-Husseini
Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.
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公开(公告)号：US20200327914A1
公开(公告)日：2020-10-15
申请号：US16914310
申请日：2020-06-27
Applicant: Intel Corporation
Inventor： Navindra Navaratnam , Nasser A. Kurd , Bee Min Teng , Raymond Chong , Nasirul I. Chowdhury , Ali M. El-Husseini
Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.
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公开(公告)号：US11290059B2
公开(公告)日：2022-03-29
申请号：US16714390
申请日：2019-12-13
Applicant: Intel Corporation
Inventor： Khang Choong Yong , Raymond Chong , Ramaswamy Parthasarathy , Stephen Hall , Chin Lee Kuan
Abstract: An apparatus is provided which comprises: a crystal having an input and an output; a first interconnect line having first and second ends, wherein the first end is coupled to the input; a second interconnect line having first and second ends, wherein the first end is coupled to the output; a first capacitor coupled to the input and ground; and a second capacitor coupled to the second end of the second interconnect line. An apparatus is provided which comprises: a high pass filter; a pair of AC coupling capacitors coupled to the high pass filter; a low pass filter coupled to the pair of AC coupling capacitors; and an analog to digital converter (ADC) coupled to the low pass filter.
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公开(公告)号：US10854249B2
公开(公告)日：2020-12-01
申请号：US16914310
申请日：2020-06-27
Applicant: Intel Corporation
Inventor： Navindra Navaratnam , Nasser A. Kurd , Bee Min Teng , Raymond Chong , Nasirul I. Chowdhury , Ali M. El-Husseini
Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.
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公开(公告)号：US10516366B2
公开(公告)日：2019-12-24
申请号：US16237093
申请日：2018-12-31
Applicant: Intel Corporation
Inventor： Khang Choong Yong , Raymond Chong , Ramaswamy Parthasarathy , Stephen Hall , Chin Lee Kuan
Abstract: An apparatus is provided which comprises: a crystal having an input and an output; a first interconnect line having first and second ends, wherein the first end is coupled to the input; a second interconnect line having first and second ends, wherein the first end is coupled to the output; a first capacitor coupled to the input and ground; and a second capacitor coupled to the second end of the second interconnect line. An apparatus is provided which comprises: a high pass filter; a pair of AC coupling capacitors coupled to the high pass filter; a low pass filter coupled to the pair of AC coupling capacitors; and an analog to digital converter (ADC) coupled to the low pass filter.
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Patent Agency Ranking
公开(公告)号：US20240364333A1
公开(公告)日：2024-10-31
申请号：US18140481
申请日：2023-04-27
Applicant: Intel Corporation
Inventor： Raymond Chong
IPC: H03K17/693
CPC classification number: H03K17/693 , H03K19/017509
Abstract: Multiplexing circuitry comprises first switch and second switches coupled in series between a first node to receive a first supply voltage and a second node to provide an output voltage, and third and fourth switches coupled in series between a third node to receive a second supply voltage and the second node. First circuitry is to generate a first switch control signal to operate the first switch. Second circuitry is to generate a second switch control signal to operate the third switch. A first driver circuit is to generate a third switch control signal to operate the second switch. A second driver circuit is to generate a fourth switch control signal to operate the fourth switch. In a cross-coupled arrangement, the third switch control signal is based on the second switch control signal, and the fourth switch control is based on the second switch control signal.
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公开(公告)号：US20200143853A1
公开(公告)日：2020-05-07
申请号：US16178346
申请日：2018-11-01
Applicant: Intel Corporation
Inventor： Navindra Navaratnam , Nasser A. Kurd , Bee Min Teng , Raymond Chong , Nasirul I. Chowdhury , Ali M. El-Husseini
Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.
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公开(公告)号：US10171033B2
公开(公告)日：2019-01-01
申请号：US15469499
申请日：2017-03-25
Applicant: INTEL CORPORATION
Inventor： Khang Choong Yong , Raymond Chong , Ramaswamy Parthasarathy , Stephen Hall , Chin Lee Kuan
Abstract: An apparatus is provided which comprises: a crystal having an input and an output; a first interconnect line having first and second ends, wherein the first end is coupled to the input; a second interconnect line having first and second ends, wherein the first end is coupled to the output; a first capacitor coupled to the input and ground; and a second capacitor coupled to the second end of the second interconnect line. An apparatus is provided which comprises: a high pass filter; a pair of AC coupling capacitors coupled to the high pass filter; a low pass filter coupled to the pair of AC coupling capacitors; and an analog to digital converter (ADC) coupled to the low pass filter.
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公开(公告)号：US11183226B2
公开(公告)日：2021-11-23
申请号：US17107704
申请日：2020-11-30
Applicant: Intel Corporation
Inventor： Navindra Navaratnam , Nasser A. Kurd , Bee Min Teng , Raymond Chong , Nasirul I. Chowdhury , Ali M. El-Husseini
Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.
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公开(公告)号：US11037607B2
公开(公告)日：2021-06-15
申请号：US16220523
申请日：2018-12-14
Applicant: Intel Corporation
Inventor： Raymond Chong , Bee Min Teng , Christopher Mozak
IPC: G01R19/00 , G11C7/00 , G11C7/06 , H03K3/037 , G11C7/10 , H04L7/00 , G11C11/16 , H04B1/16 , G11C7/08
Abstract: Described is an apparatus to widen or improve a common mode range of a strong arm latch (SAL). In some embodiments, the SAL comprises a master-slave architecture with a common latch. The apparatus includes: a sampler to sample an input with a first clock, and to provide a sampled output on a node. The SAL is to receive the sampled output on the node, and to sample the sampled output according to a second clock. The apparatus comprises a digital-to-analog converter (DAC) coupled to the node, wherein the DAC is to adjust a common mode of the sampled output according to a digital control to the DAC.
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