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公开(公告)号：US11264160B2
公开(公告)日：2022-03-01
申请号：US16402467
申请日：2019-05-03
Applicant: Intel Corporation
Inventor： Eng Huat Goh , Jiun Hann Sir , Min Suet Lim , Chin Lee Kuan , Siew Fong Yap
Abstract: An electronic device comprises an air core inductor including an electronic semiconductor package including a first portion of the air core inductor internal to the electronic semiconductor package; and an electrically conductive layer arranged on a first external surface of the electronic semiconductor package and electrically connected as a second portion of the air core inductor.
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公开(公告)号：US11031359B2
公开(公告)日：2021-06-08
申请号：US16462197
申请日：2017-11-20
Applicant: Intel Corporation
Inventor： Jenny Shio Yin Ong , Tin Poay Chuah , Chin Lee Kuan
Abstract: A capacitor loop substrate assembly may include a substrate with a loop shape, one or more capacitors or other electronic components on the substrate, and an opening in the substrate to allow the capacitor loop substrate assembly to be coupled to an integrated circuit package, such as a package including a die. Interconnects and/or contacts for interconnects may be formed in an integrated circuit package to couple the capacitor loop substrate assembly to the integrated circuit package.
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公开(公告)号：US10719109B2
公开(公告)日：2020-07-21
申请号：US15627159
申请日：2017-06-19
Applicant: Intel Corporation
Inventor： Amit K. Jain , Chin Lee Kuan , Sameer Shekhar
IPC: G06F1/26
Abstract: Described is an apparatus which comprises: a power supply node; a plurality of inductors inductively coupled with one another, wherein at least one inductor of the plurality is electrically coupled to the power supply node; a plurality of loads; and a plurality of capacitors coupled to the plurality of inductors, respectively, and also coupled to the plurality of loads, respectively.
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公开(公告)号：US20200027639A1
公开(公告)日：2020-01-23
申请号：US16402467
申请日：2019-05-03
Applicant: Intel Corporation
Inventor： Eng Huat Goh , Jiun Hann Sir , Min Suet Lim , Chin Lee Kuan , Siew Fong Yap
Abstract: An electronic device comprises an air core inductor including an electronic semiconductor package including a first portion of the air core inductor internal to the electronic semiconductor package; and an electrically conductive layer arranged on a first external surface of the electronic semiconductor package and electrically connected as a second portion of the air core inductor.
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公开(公告)号：US11749606B2
公开(公告)日：2023-09-05
申请号：US17371293
申请日：2021-07-09
Applicant: Intel Corporation
Inventor： Amit Kumar Jain , Sameer Shekhar , Chin Lee Kuan , Kevin Joseph Doran , Dong-Ho Han
IPC: H01L23/538 , H01L49/02 , H01L23/00
CPC classification number: H01L23/5381 , H01L23/5383 , H01L28/20 , H01L28/40 , H01L23/5384 , H01L24/16 , H01L2224/16225
Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate; a bridge, embedded in the package substrate, wherein the bridge includes an integral passive component, and wherein a surface of the bridge include first contacts in a first interconnect area and second contacts in a second interconnect area; a first die coupled to the passive component via the first contacts in the first interconnect area; and a second die coupled to the second contacts in the second interconnect area.
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Patent Agency Ranking
6.发明授权公开(公告)号：US11437294B2
公开(公告)日：2022-09-06
申请号：US16059513
申请日：2018-08-09
Applicant: Intel Corporation
Inventor： Sameer Shekhar , Amit Kumar Jain , Kaladhar Radhakrishnan , Jonathan P. Douglas , Chin Lee Kuan
IPC: H01L23/367 , H01L23/498 , H01L23/522 , H01L23/00 , G06F1/20
Abstract: Embodiments disclosed herein include electronics packages with improved thermal pathways. In an embodiment, an electronics package includes a package substrate. In an embodiment, the package substrate comprises a plurality of backside layers, a plurality of front-side layers, and a core layer between the plurality of backside layers and the plurality of front-side layers. In an embodiment, an inductor is embedded in the plurality of backside layers. In an embodiment, a plurality of bumps are formed over the front-side layers and thermally coupled to the inductor. In an embodiment, the plurality of bumps are thermally coupled to the core layer by a plurality of vias.
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公开(公告)号：US11380623B2
公开(公告)日：2022-07-05
申请号：US15939162
申请日：2018-03-28
Applicant: Intel Corporation
Inventor： Sameer Shekhar , Chin Lee Kuan , Amit Kumar Jain
IPC: H01L23/552 , H01L23/00 , H01L23/498 , H01F27/36 , H05K9/00
Abstract: Embodiments herein relate to a package having a substrate with a core layer with a plurality of conductors coupling a first side of the core layer with a second side of the core layer, and a shield within the core layer that separates a first conductor of the plurality of conductors from a second conductor of the plurality of conductors where the shield is to reduce electromagnetic interference received by the second conductor that is generated by the first conductor. Embodiments may also be related to a package having a substrate with a through hole via through the substrate, where an EMI protective material is applied to a surface of the substrate that forms the via to shield an inner portion of the via.
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公开(公告)号：US11290059B2
公开(公告)日：2022-03-29
申请号：US16714390
申请日：2019-12-13
Applicant: Intel Corporation
Inventor： Khang Choong Yong , Raymond Chong , Ramaswamy Parthasarathy , Stephen Hall , Chin Lee Kuan
Abstract: An apparatus is provided which comprises: a crystal having an input and an output; a first interconnect line having first and second ends, wherein the first end is coupled to the input; a second interconnect line having first and second ends, wherein the first end is coupled to the output; a first capacitor coupled to the input and ground; and a second capacitor coupled to the second end of the second interconnect line. An apparatus is provided which comprises: a high pass filter; a pair of AC coupling capacitors coupled to the high pass filter; a low pass filter coupled to the pair of AC coupling capacitors; and an analog to digital converter (ADC) coupled to the low pass filter.
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公开(公告)号：US10516366B2
公开(公告)日：2019-12-24
申请号：US16237093
申请日：2018-12-31
Applicant: Intel Corporation
Inventor： Khang Choong Yong , Raymond Chong , Ramaswamy Parthasarathy , Stephen Hall , Chin Lee Kuan
Abstract: An apparatus is provided which comprises: a crystal having an input and an output; a first interconnect line having first and second ends, wherein the first end is coupled to the input; a second interconnect line having first and second ends, wherein the first end is coupled to the output; a first capacitor coupled to the input and ground; and a second capacitor coupled to the second end of the second interconnect line. An apparatus is provided which comprises: a high pass filter; a pair of AC coupling capacitors coupled to the high pass filter; a low pass filter coupled to the pair of AC coupling capacitors; and an analog to digital converter (ADC) coupled to the low pass filter.
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公开(公告)号：US20190304915A1
公开(公告)日：2019-10-03
申请号：US16446920
申请日：2019-06-20
Applicant: Intel Corporation
Inventor： Amit Kumar Jain , Sameer Shekhar , Chin Lee Kuan , Kevin Joseph Doran , Dong-Ho Han
IPC: H01L23/538 , H01L49/02
Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate; a bridge, embedded in the package substrate, wherein the bridge includes an integral passive component, and wherein a surface of the bridge include first contacts in a first interconnect area and second contacts in a second interconnect area; a first die coupled to the passive component via the first contacts in the first interconnect area; and a second die coupled to the second contacts in the second interconnect area.
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