公开(公告)号：US20240008290A1

公开(公告)日：2024-01-04

申请号：US17855626

申请日：2022-06-30

Applicant: INTEL CORPORATION

Inventor： Chia-Ching LIN ,  Shriram SHIVARAMAN ,  Kevin P. O'BRIEN ,  Ashish Verma PENUMATCHA ,  Chelsey DOROW ,  Kirby MAXEY ,  Carl H. NAYLOR ,  Sudarat LEE ,  Uygar E. AVCI ,  Sou-Chi CHANG

IPC: H01L27/11507 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L23/48

CPC classification number: H01L27/11507 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/78391 ,  H01L23/481

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques directed to creating back end of line 2D transistors that include a metal-ferroelectric-metal-insulator-semiconductor structure used as a memory cell. In embodiments, a combination wet etch and dry etch process may be used to form the 2D transistors. Other embodiments may be described and/or claimed.

公开(公告)号：US20230116719A1

公开(公告)日：2023-04-13

申请号：US17485305

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Elijah V. KARPOV ,  Sou-Chi CHANG ,  Uygar E. AVCI ,  Shriram SHIVARAMAN

IPC: H01L27/11507 ,  H01L27/11514

Abstract: Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to memory devices with nitride-based ferroelectric materials. Other embodiments may be disclosed or claimed.

公开(公告)号：US20230097736A1

公开(公告)日：2023-03-30

申请号：US17485308

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Shriram SHIVARAMAN ,  Sou-Chi CHANG ,  Nazila HARATIPOUR ,  Uygar E. AVCI ,  Jason PECK ,  Nafees A. KABIR ,  Sarah ATANASOV

IPC: H01L27/11507 ,  G11C11/22 ,  H01L27/11504

Abstract: Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to ferroelectric random access memory (FRAM) devices with an enhanced capacitor architecture. Other embodiments may be disclosed or claimed.

公开(公告)号：US20220208777A1

公开(公告)日：2022-06-30

申请号：US17134279

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Nazila HARATIPOUR ,  Sou-Chi CHANG ,  Shriram SHIVARAMAN ,  Uygar E. AVCI ,  Jack T. KAVALIEROS

IPC: H01L27/11514 ,  H01L23/522 ,  H01L27/11507

Abstract: A memory device comprises an access transistor comprising a bitline and a wordline. A series of alternating plate lines and an insulating material is over the access transistor, the plate lines comprising an adhesion material on a top and a bottom thereof and a metal material in between the adhesion material, the metal material having one or more voids therein. Two or more ferroelectric capacitors is over the access transistor and through the series of alternating plate lines and an insulating material such that a first one of the ferroelectric capacitors is coupled to a first one of the plate lines and a second one of the ferroelectric capacitors is coupled to a second one of the plate lines, and wherein the two or more ferroelectric capacitors are each coupled to and controlled by the access transistor. A plurality of vias each land on a respective one of the plate lines, wherein the plurality of vias comprises a same metal material as the plate lines.

公开(公告)号：US20220199635A1

公开(公告)日：2022-06-23

申请号：US17129851

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Shriram SHIVARAMAN ,  Uygar E. AVCI ,  Sou-Chi CHANG ,  Nazila HARATIPOUR ,  Jack T. KAVALIEROS

IPC: H01L27/11514 ,  H01L23/522 ,  H01L27/11507

Abstract: Plate line architectures for 3D-Ferroelectric Random Access Memory (3D-FRAM) are described. In an example, a memory device includes a plurality of bitlines along a first direction and a plurality of wordlines along a second direction orthogonal to the first direction. An access transistor is at an intersection of a first one of the bitlines and a first one of the wordlines. A series of alternating plate lines and insulating material are fabricated over the access transistor. Two or more ferroelectric capacitors are over the access transistor and through the series of alternating plate lines and an insulating material such that a first one of the ferroelectric capacitors is coupled to a first one of the plate lines and a second one of the ferroelectric capacitors is coupled to a second one of the plate lines, and wherein the two or more ferroelectric capacitors are each coupled to and controlled by the access transistor.

公开(公告)号：US20230100860A1

公开(公告)日：2023-03-30

申请号：US17485306

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Sou-Chi CHANG ,  Nazila HARATIPOUR ,  Shriram SHIVARAMAN ,  Uygar E. AVCI ,  Sarah ATANASOV ,  Christopher M. NEUMANN

IPC: H01L27/11507 ,  H01L27/108 ,  H01L25/065

Abstract: Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to memory devices utilizing dead-layer-free materials to reduce disturb effects. Other embodiments may be described or claimed.

公开(公告)号：US20230097184A1

公开(公告)日：2023-03-30

申请号：US17485310

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Sarah ATANASOV ,  Nazila HARATIPOUR ,  Sou-Chi CHANG ,  Shriram SHIVARAMAN ,  Uygar E. AVCI

IPC: H01L49/02 ,  H01L27/11507

Abstract: Embodiments of the present disclosure are directed to advanced integrated circuit structure fabrication and, in particular, integrated circuits with high dielectric constant (HiK) interfacial layering between an electrode and a ferroelectric (FE) or anti-ferroelectric (AFE) layer. Other embodiments may be disclosed or claimed.

公开(公告)号：US20220149192A1

公开(公告)日：2022-05-12

申请号：US17093452

申请日：2020-11-09

Applicant: Intel Corporation

Inventor： Kirby MAXEY ,  Ashish Verma PENUMATCHA ,  Carl NAYLOR ,  Chelsey DOROW ,  Kevin P. O'BRIEN ,  Shriram SHIVARAMAN ,  Tanay GOSAVI ,  Uygar E. AVCI ,  Sudarat LEE

IPC: H01L29/76 ,  H01L29/24 ,  H01L29/786 ,  H01L29/66

Abstract: Thin film transistors having electrostatic double gates are described. In an example, an integrated circuit structure includes an insulator layer above a substrate. A first gate stack is on the insulator layer. A 2D channel material layer is on the first gate stack. A second gate stack is on a first portion of the 2D channel material layer, the second gate stack having a first side opposite a second side. A first conductive contact is adjacent the first side of the second gate stack, the first conductive contact on a second portion of the 2D channel material layer. A second conductive contact is adjacent the second side of the second gate stack, the second conductive contact on a third portion of the 2D channel material layer. A gate electrode of the first gate stack extends beneath a portion of the first conductive contact and beneath a portion of the second conductive contact.

公开(公告)号：US20190393223A1

公开(公告)日：2019-12-26

申请号：US16480948

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Van H. LE ,  Gilbert William DEWEY ,  Rafael RIOS ,  Jack T. KAVALIEROS ,  Yih WANG ,  Shriram SHIVARAMAN

IPC: H01L27/108 ,  H01L27/13 ,  G11C11/4096 ,  G11C11/408 ,  H01L29/786 ,  H01L21/768 ,  H01L21/02 ,  H01L29/40 ,  H01L21/311 ,  H01L49/02 ,  H01L29/423 ,  H01L29/66 ,  H01L29/24 ,  H01L29/22

Abstract: A charge storage memory is described based on a vertical shared gate thin-film transistor. In one example, a memory cell structure includes a capacitor to store a charge, the state of the charge representing a stored value, and an access transistor having a drain coupled to a bit line to read the capacitor state, a vertical gate coupled to a word line to write the capacitor state, and a drain coupled to the capacitor to charge the capacitor from the drain through the gate, wherein the gate extends from the word line through metal layers of an integrated circuit.

公开(公告)号：US20230102900A1

公开(公告)日：2023-03-30

申请号：US17485162

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Nafees A. KABIR ,  Shriram SHIVARAMAN ,  Seung Hoon SUNG ,  Uygar E. AVCI

IPC: H01L29/786 ,  H01L29/78 ,  H01L29/66 ,  H01L21/4763

Abstract: A method of fabricating an integrated circuit structure comprises depositing an oxide insulator layer over a substrate having fins. A gate trench is formed within the oxide insulator layer with the fins extending above a surface of the oxide insulator layer within the gate trench. A semiconducting oxide material is deposited to conformally cover the oxide insulator layer, including on top surfaces and sidewalls of both the gate trench and the fins. A gate material is deposited to conformally cover the semiconducting oxide material, including on top surfaces and sidewalls of both the gate trench and the fins. An angled etch is performed to remove the gate material selective to the semiconducting oxide material from sidewalls of the gate trench, but not from sidewalls of the fins.