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    Methods and apparatus to provide for efficient and secure software updates
    4.
    发明授权
    Methods and apparatus to provide for efficient and secure software updates 有权

    公开(公告)号：US10715335B2

    公开(公告)日：2020-07-14

    申请号：US16026657

    申请日：2018-07-03

    Applicant: Intel Corporation

    Inventor： Steffen Schulz ,  Rafael Misoczki ,  Manoj R. Sastry ,  Jesse Walker

    IPC: H04L29/06 ,  H04L9/32 ,  H04L29/08 ,  H04L9/08 ,  G06F8/65 ,  H04L9/14 ,  H04L9/30

    Abstract: In a method for validating software updates, a data processing system contains a current version of a software component. The data processing system saves at least first and second current advance keys (AKs). After saving the current AKs, the data processing system receives an update package for a new version of the software component. The data processing system extracts a digital signature and two or more new AKs from the update package. The data processing system uses at least one current AK to determine whether the digital signature is valid. In response to a determination that the digital signature is valid, the data processing system uses a software image from the update package to update the software component, and the data processing system saves the new AKs, for subsequent utilization as the current AKs.

    HASH-BASED SIGNATURE BALANCING
    5.
    发明申请
    HASH-BASED SIGNATURE BALANCING 审中-公开

    公开(公告)号：US20180091309A1

    公开(公告)日：2018-03-29

    申请号：US15277462

    申请日：2016-09-27

    Applicant: Intel Corporation

    Inventor： Rafael Misoczki ,  Steffen Schulz ,  Manoj R. Sastry ,  Santosh Ghosh ,  Li Zhao

    IPC: H04L9/32

    CPC classification number: H04L9/3247 ,  H04L9/3242 ,  H04L9/3252 ,  H04L2209/30 ,  H04L2209/38

    Abstract: One embodiment provides a signer device. The signer device includes hash signature control logic and signer signature logic. The hash signature control logic is to retrieve a first nonce, to concatenate the first nonce and a message to be transmitted and to determine whether a first message representative satisfies a target threshold. The signer signature logic is to generate a first transmitted signature based, at least in part, on the first message representative, if the first message representative satisfies the target threshold. The hash signature control logic is to retrieve a second nonce, concatenate the second nonce and the message to be transmitted and to determine whether a second message representative satisfies the target threshold, if the first message representative does not satisfy the target threshold.

    System, Apparatus And Method For Key Provisioning Delegation
    6.
    发明申请
    System, Apparatus And Method For Key Provisioning Delegation 审中-公开

    公开(公告)号：US20170272415A1

    公开(公告)日：2017-09-21

    申请号：US15070166

    申请日：2016-03-15

    Applicant: Intel Corporation

    Inventor： Meiyuan Zhao ,  Jesse Walker ,  Xiruo Liu ,  Steffen Schulz ,  Jianqing Zhang

    IPC: H04L29/06

    CPC classification number: H04L63/061 ,  H04L63/0807 ,  H04L63/0884 ,  H04W12/06

    Abstract: In one embodiment, a computing device includes at least one hardware processor to execute instructions, a network interface to enable communication with a second computing device and a third computing device, and at least one storage medium. Such medium may store instructions that when executed by the computing device enable the computing device to request delegation of a key provisioning privilege for the second computing device from the third computing device via a parent-guardian delegation protocol comprising a three-party key distribution protocol with the second computing device and the third computing device, the three-party key distribution protocol having interposed therein a two-party authenticated key exchange protocol between the computing device and the third computing device. Other embodiments are described and claimed.

    Dynamic configuration and peripheral access in a processor
    7.
    发明授权
    Dynamic configuration and peripheral access in a processor 有权

    公开(公告)号：US09710404B2

    公开(公告)日：2017-07-18

    申请号：US14666087

    申请日：2015-03-23

    Applicant: Intel Corporation

    Inventor： Steffen Schulz ,  Patrick Koeberl

    IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/14 ,  G06F11/30 ,  G06F11/07

    CPC classification number: G06F12/145 ,  G06F11/073 ,  G06F11/0757 ,  G06F11/3034 ,  G06F11/3037 ,  G06F12/1483 ,  G06F21/00 ,  G06F2212/1052

    Abstract: In various implementations, a system includes a memory, a processor, and an execution-aware memory protection unit (EA-MPU). The EA-MPU is configured to regulate memory access by the processor based at least on the identity of a subject executable that requests access, and on the address to which access is requested, and on permissions information that identifies which subject executables are to be granted access to each of several memory regions. In various implementations, the permissions information itself is stored among the several memory regions. Various configurations of the permissions information can be used to provide shared memory regions for communication among two or more stand-alone trusted software modules, to protect access to devices accessible through memory-mapped I/O (MMIO), to implement a flexible watchdog timer, to provide security for software updates, to provide dynamic root of trust measurement services, and/or to support an operating system.

    ENABLING SECURE STATE-CLEAN DURING CONFIGURATION OF PARTIAL RECONFIGURATION BITSTREAMS ON FPGA
    10.
    发明申请
    ENABLING SECURE STATE-CLEAN DURING CONFIGURATION OF PARTIAL RECONFIGURATION BITSTREAMS ON FPGA 有权

    公开(公告)号：US20210110069A1

    公开(公告)日：2021-04-15

    申请号：US17129250

    申请日：2020-12-21

    Applicant: Intel Corporation

    Inventor： Alpa Trivedi ,  Scott Weber ,  Steffen Schulz ,  Patrick Koeberl

    IPC: G06F21/76 ,  G06F21/57 ,  G06F21/53 ,  G06F21/30

    Abstract: An apparatus to facilitate enabling secure state-clean during configuration of partial reconfiguration bitstreams on accelerator devices is disclosed. The apparatus includes a security engine to receive an incoming partial reconfiguration (PR) bitstream corresponding to a new PR persona to configure a region of the apparatus; perform, as part of a PR configuration sequence for the new PR persona, a first clear operation to clear previously-set persona configuration bits in the region; perform, as part of the PR configuration sequence subsequent to the first clear operation, a set operation to set new persona configuration bits in the region; and perform, as part of the PR configuration sequence, a second clear operation to clear memory blocks of the region that became unfrozen subsequent to the set operation, the second clear operation performed using a persona-dependent mask corresponding to the new PR persona.

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