公开(公告)号：US20240266349A1

公开(公告)日：2024-08-08

申请号：US18433779

申请日：2024-02-06

Applicant: IMEC VZW

Inventor： Gioele Mirabelli ,  Juergen Boemmels ,  Julien Ryckaert

IPC: H01L27/092 ,  H01L23/528 ,  H01L27/06 ,  H10B10/00

CPC classification number: H01L27/092 ,  H01L23/5286 ,  H01L27/0688 ,  H10B10/12

Abstract: This disclosure relates to complementary field effect transistor (CFET) devices, and provides improved routability of the transistor structures in a CFET cell. The disclosure presents a CFET cell that includes a first transistor structure in a first tier and a second transistor structure in a second tier above the first tier. A first power rail is arranged below the first tier and connected to the first transistor structure from below, and a second power rail is formed in a first metal layer and connected to the second transistor structure from a first side. A set of signal routing lines formed in a second metal layer above the second tier is connected to the first and second transistor structure from above. Further, a signal routing structure formed in a metal zero (M0) layer is connected to the first transistor structure and/or to the second transistor structure from a second side.

公开(公告)号：US20240290660A1

公开(公告)日：2024-08-29

申请号：US18529121

申请日：2023-12-05

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Gaspard Hiblot ,  Gioele Mirabelli

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823475 ,  H01L21/823481 ,  H01L27/088

Abstract: Integrated circuit chips and method for making integrated circuit chips are provided. The method includes providing a semiconductor substrate, forming a device layer including a forksheet device on the substrate and providing the substrate with a substrate part of a dielectric wall of the forksheet device, a first shallow trench isolation and a second shallow trench isolation. The method also includes contacting a source or drain contact and extending into the substrate between the first shallow trench isolation and the dielectric wall, then removing the substrate material so as to expose an end of the dielectric wall, the first surface, and the second surface, then obtaining a first spacer and a second spacer, so as to obtain a trench, wherein the end of the dielectric wall is exposed to the trench, then depositing an electrically insulating material in the trench so as to form an extension.

公开(公告)号：US20240213312A1

公开(公告)日：2024-06-27

申请号：US18514753

申请日：2023-11-20

Applicant: IMEC VZW

Inventor： Gaspard Hiblot ,  Boon Teik Chan ,  Gioele Mirabelli

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0649 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: An integrated circuit device and method for forming the integrated circuit device are provided. The method includes: a) forming a semiconductor device on a frontside of a substrate comprising: a device layer on the frontside of the substrate, the device layer comprising a first active device, the substrate comprising: shallow trench isolation structures and a via filled with a sacrificial plug extending through the substrate material in a first separating portion; b) removing the substrate material from a backside of the substrate; c) depositing a liner covering the backside of the substrate; d) anisotropically etching the liner so as to expose a first end of the sacrificial plug, while retaining at least part of the liner in the separating portions; e) removing the sacrificial plug selectively with respect to the liner; and f) providing an electrically conductive material in the via, electrically coupled to a buried power rail.

公开(公告)号：US20250107199A1

公开(公告)日：2025-03-27

申请号：US18889130

申请日：2024-09-18

Applicant: Imec vzw

Inventor： Boon Teik Chan ,  Gaspard Hiblot ,  Gioele Mirabelli

IPC: H01L29/66 ,  H01L21/8234 ,  H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A method includes forming an isolation structure in a substrate, forming a fin-shaped structure from the substrate, a bottom sacrificial layer, and a stack of layers, forming a dummy gate over a channel region of the fin-shaped structure, forming a recess at a source/drain region of the fin-shaped structure, the source/drain recess extending through the stack of layers and the bottom sacrificial layer, removing the bottom sacrificial layer thereby forming a void, depositing a bottom dielectric insulation layer in the void, extending the recess into the substrate, depositing a plug in the recess, forming an epitaxial structure to form a source/drain feature above the plug in the recess, removing the dummy gate, removing the sacrificial layers in the channel region, forming a replacement metal gate around the channel layers, thinning the substrate, etching the plug to expose the source/drain feature, and forming a source/drain electrical contact at the source/drain feature.

公开(公告)号：US20250096037A1

公开(公告)日：2025-03-20

申请号：US18889580

申请日：2024-09-19

Applicant: Imec vzw

Inventor： Gaspard Hiblot ,  Gioele Mirabelli

IPC: H01L21/768 ,  H01L29/66

Abstract: A method for forming a semiconductor device includes forming a trench for a buried interconnect structure between first and second fin structures and lining the trench with a dielectric layer. The method also includes etching a contact opening in a first portion of the dielectric layer adjacent a first region of the first fin structure while masking the second portion of the dielectric layer adjacent a second region of the second fin structure directly opposite the first region. The method also includes forming a local interconnect trench extending between the first and second regions, where the second portion of the dielectric layer partitions the local interconnect trench into first and second trench portions. The method also includes forming first and second local interconnects in the first and second trench portions. The first and second local interconnects are separated by the second portion of the dielectric layer.

公开(公告)号：US20240321889A1

公开(公告)日：2024-09-26

申请号：US18608650

申请日：2024-03-18

Applicant: IMEC VZW

Inventor： Gaspard Hiblot ,  Gioele Mirabelli

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L27/0922 ,  H01L21/8221 ,  H01L21/823871 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: The disclosed technology generally relates to a complementary field effect transistor (CFET) cell. In one aspect, the CFET cell includes: a first transistor structure arranged in a first tier of the CFET cell; a second transistor structure arranged in a second tier of the CFET cell above the first tier; a set of top signal routing lines formed in a first metal layer above the second tier and connected to the first and the second transistor structures from above; and at least one bottom signal routing line formed in a second metal layer below the first tier and connected to the first transistor structure from below. The disclosed technology also generally relates to a method of fabricating a CFET cell.