公开(公告)号：US20240290660A1

公开(公告)日：2024-08-29

申请号：US18529121

申请日：2023-12-05

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Gaspard Hiblot ,  Gioele Mirabelli

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823475 ,  H01L21/823481 ,  H01L27/088

Abstract: Integrated circuit chips and method for making integrated circuit chips are provided. The method includes providing a semiconductor substrate, forming a device layer including a forksheet device on the substrate and providing the substrate with a substrate part of a dielectric wall of the forksheet device, a first shallow trench isolation and a second shallow trench isolation. The method also includes contacting a source or drain contact and extending into the substrate between the first shallow trench isolation and the dielectric wall, then removing the substrate material so as to expose an end of the dielectric wall, the first surface, and the second surface, then obtaining a first spacer and a second spacer, so as to obtain a trench, wherein the end of the dielectric wall is exposed to the trench, then depositing an electrically insulating material in the trench so as to form an extension.

公开(公告)号：US20240213312A1

公开(公告)日：2024-06-27

申请号：US18514753

申请日：2023-11-20

Applicant: IMEC VZW

Inventor： Gaspard Hiblot ,  Boon Teik Chan ,  Gioele Mirabelli

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0649 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: An integrated circuit device and method for forming the integrated circuit device are provided. The method includes: a) forming a semiconductor device on a frontside of a substrate comprising: a device layer on the frontside of the substrate, the device layer comprising a first active device, the substrate comprising: shallow trench isolation structures and a via filled with a sacrificial plug extending through the substrate material in a first separating portion; b) removing the substrate material from a backside of the substrate; c) depositing a liner covering the backside of the substrate; d) anisotropically etching the liner so as to expose a first end of the sacrificial plug, while retaining at least part of the liner in the separating portions; e) removing the sacrificial plug selectively with respect to the liner; and f) providing an electrically conductive material in the via, electrically coupled to a buried power rail.

公开(公告)号：US10825806B2

公开(公告)日：2020-11-03

申请号：US16215492

申请日：2018-12-10

Applicant: IMEC vzw

Inventor： Gaspard Hiblot ,  Geert Van der Plas ,  Stefaan Van Huylenbroeck

IPC: H01L27/02 ,  H01L21/3065 ,  H01L21/768 ,  H01L23/48 ,  H01L23/60

Abstract: The disclosed technology relates to a semiconductor integrated circuit that comprises a semiconductor device which has a port to be protected from Plasma-Induced Damage due to electric charge that may accumulate at the port during a plasma-processing step, and a protection circuit that is provided to the integrated circuit. In one aspect, the protection circuit comprises a discharge path, a control terminal, and a plasma pick-up antenna connected to the control terminal. The protection circuit further comprises a bipolar transistor which has a base connected to the control terminal. Such protection circuit is much more efficient in allowing charge transfer from the device port to a reference voltage terminal.

公开(公告)号：US20190074231A1

公开(公告)日：2019-03-07

申请号：US16121369

申请日：2018-09-04

Applicant: IMEC VZW

Inventor： Gaspard Hiblot ,  Geert Van der Plas ,  Stefaan Van Huylenbroeck

IPC: H01L21/66 ,  H01L21/265 ,  G01L1/18

Abstract: An example embodiment may include a sensor for monitoring and/or measuring stress in a semiconductor component. The component may include a substrate formed of a semiconductor material. The substrate may include a planar main surface. The sensor may include at least one slanted surface of the substrate material, the slanted surface being defined by an oblique inclination angle with respect to the main surface of the substrate. The sensor may also include at least one straight resistive path extending on at least part of the slanted surface and a plurality of contacts and terminals for accessing the at least one resistive path. The contacts and terminals may allow for the measurement of an electrical resistance of the resistive path and an assessment of a shear stress in a plane that is not parallel to the main surface of the substrate.

公开(公告)号：US12154830B2

公开(公告)日：2024-11-26

申请号：US17580020

申请日：2022-01-20

Applicant: IMEC vzw

Inventor： Gaspard Hiblot ,  Anshul Gupta ,  Geert Van Der Plas

IPC: H01L21/8234 ,  H01L27/088

Abstract: A method of producing a gate cut in a semiconductor component is provided. In one aspect, an array of nano-sized semiconductor fins is processed on a semiconductor substrate. Rails may be buried in the substrate and in a layer of dielectric material that isolates neighboring fins from each other. The rails may extend in the direction of the fins and each rail may be situated between two adjacent fins. The rails may be buried power rails for enabling the formation of a power delivery network at the back of an integrated circuit chip. At the front side of the substrate, one or more gate structures are produced. The gate structures extend transversally, or perpendicularly, with respect to the fins and the rails. A gate cut is produced by forming an opening from the back side of the substrate, and removing a portion of the gate structure at the bottom of the opening, thereby creating a gate cut that is aligned to the sidewalls of the rail. In another aspect, a semiconductor component, such as an integrated circuit, includes a gate cut that is aligned to the sidewalls of a buried contact rail.

公开(公告)号：US20210074830A1

公开(公告)日：2021-03-11

申请号：US17013230

申请日：2020-09-04

Applicant: IMEC VZW

Inventor： Gaspard Hiblot ,  Sylvain Baudot

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: A method for electrically isolating a vertical nanowire on at least one location in the nanowire. The method comprises providing a substrate, forming a vertical nanowire stack on the substrate. The stack comprises at least one nanowire section of a first material. A sacrificial section of a second material is provided in the vertical nanowire stack on the at least one location. The second material is selected such that it can be selectively removed with respect to the first material. The method, moreover, comprises creating at least one interconnect to the at least one nanowire section which should be isolated, removing the at least one sacrificial section and replacing it with an isolating section after creating the interconnect.

公开(公告)号：US10903335B2

公开(公告)日：2021-01-26

申请号：US16408971

申请日：2019-05-10

Applicant: IMEC VZW

Inventor： Gaspard Hiblot ,  Sylvain Baudot ,  Hans Mertens ,  Julien Jussot

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L29/06 ,  H01L29/786 ,  H01L29/775 ,  H01L29/40 ,  H01L29/78 ,  H01L29/423

Abstract: A method of forming aligned gates for horizontal nanowires or nanosheets, comprising: providing a wafer which comprises at least one fin of sacrificial layers alternated with functional layers, and a dummy gate covering a section of the fin between a first end and a second end; at least partly removing the sacrificial layers at the first end and the second end thereby forming a void between the functional layers at the first and end such that the void is partly covered by the dummy gate; providing resist material which oxidizes upon EUV exposure; exposing the wafer to EUV light; selectively removing the dummy gate and the unexposed resist; forming a gate between the functional layers and between the exposed resist at the first end and at the second end.

公开(公告)号：US20200373242A1

公开(公告)日：2020-11-26

申请号：US16874446

申请日：2020-05-14

Applicant: IMEC vzw

Inventor： Gaspard Hiblot ,  Geert Van Der Plas

IPC: H01L23/538 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L23/50 ,  H01L21/768

Abstract: An integrated circuit (IC) chip that includes a semiconductor substrate including active devices on its front side, and at least part of a power delivery network (PDN) on its back side, is disclosed. In one aspect, the PDN includes a power supply terminal (Vdd) and a reference terminal (Vss) at the back of the IC. A plurality of TSV (Through Semiconductor Via) connections through the substrate bring the power to the front of the substrate. A field effect transistor is integrated at the back side of the substrate, and includes a source electrode, a drain electrode, and a gate electrode, which are contacted at the back side of the substrate. The IC further includes a gate control terminal for controlling the gate voltage. The transistor is coupled between the power supply terminal and one or more of the active devices of the IC.

公开(公告)号：US20200152804A1

公开(公告)日：2020-05-14

申请号：US16676882

申请日：2019-11-07

Applicant: IMEC VZW

Inventor： Gaspard Hiblot ,  Luka Kljucar

IPC: H01L29/84 ,  H01L29/417 ,  H01L29/45 ,  H01L29/43 ,  H01L23/528 ,  G01L1/20

Abstract: A sensor for measuring mechanical stress in a layered metallization structure such as the back end of line portion of an integrated circuit die is provided. The sensor operates as a field effect transistor comprising a gate electrode, gate dielectric, channel and source and drain electrodes, wherein the gate electrode is a conductor of a first metallization level and the source and drain electrodes are two interconnect vias, connecting the channel to respective conductors in an adjacent level. At least one of the interconnect vias is formed of a material whereof the electrical resistance is sensitive to mechanical stress in the direction of the via. The sensitivity of the electrical resistance to the mechanical stress is sufficient to facilitate measurement of the stress by reading out the drain current of the transistor. The sensor thereby allows monitoring of stress in the BEOL prior to cracking.

公开(公告)号：US20200004285A1

公开(公告)日：2020-01-02

申请号：US16452143

申请日：2019-06-25

Applicant: IMEC VZW

Inventor： Gaspard Hiblot ,  Bertrand Parvais

IPC: G05F1/595

Abstract: Example embodiments relate to low-temperature voltage references using Coulomb blockade mechanisms. One embodiment includes a method of generating a reference voltage. The method includes providing a first single-electron transistor (SET) and a second SET connected in series. The method also includes biasing the first SET and the second SET using a same biasing current (Ib). Further, the method includes operating the first SET at a slope of a first Coulomb peak and the second SET at a slope of a second Coulomb peak. The slope of the first Coulomb peak and the second Coulomb peak are of the same slope type selected from a rising slope, a peak maximum, and a falling slope. The second Coulomb peak is different from the first Coulomb peak. Additionally, the method includes generating the reference voltage (Vref) based on a difference between gate-to-source voltages of the first SET (Vgs1) and the second SET (Vgs2).