公开(公告)号：US20200045285A1

公开(公告)日：2020-02-06

申请号：US16050322

申请日：2018-07-31

Applicant: Intel Corporation

Inventor： MAYURESH VARERKAR ,  STANLEY BARAN ,  MICHAEL APODACA ,  PRASOONKUMAR SURTI ,  ATSUO KUWAHARA ,  NARAYAN BISWAL ,  JILL BOYCE ,  YI-JEN CHIU ,  GOKCEN CILINGIR ,  BARNAN DAS ,  ATUL DIVEKAR ,  SRIKANTH POTLURI ,  NILESH SHAH ,  ARCHIE SHARMA

IPC: H04N13/111 ,  H04N19/597 ,  G06F3/01 ,  G06F9/38 ,  G06F15/18

Abstract: A mechanism is described for facilitating adaptive resolution and viewpoint-prediction for immersive media in computing environments. An apparatus of embodiments, as described herein, includes one or more processors to receive viewing positions associated with a user with respect to a display, and analyze relevance of media contents based on the viewing positions, where the media content includes immersive videos of scenes captured by one or more cameras. The one or more processors are further to predict portions of the media contents as relevant portions based on the viewing positions and transmit the relevant portions to be rendered and displayed.

公开(公告)号：US20210090207A1

公开(公告)日：2021-03-25

申请号：US17061296

申请日：2020-10-01

Applicant: Intel Corporation

Inventor： MICHAEL DOYLE ,  TRAVIS SCHLUESSLER ,  GABOR LIKTOR ,  ATSUO KUWAHARA ,  JEFFERSON AMSTUTZ

IPC: G06T1/20 ,  G06F16/901 ,  G06F9/38 ,  G06F9/50 ,  G06T15/00

Abstract: An apparatus comprising a sorting unit to sort primitives of a graphics image, the primitives to be grouped, each group to form a first level node of a hierarchical acceleration structure; a parallel reconfigurable clustering array to construct the hierarchical acceleration structure, the parallel reconfigurable clustering array comprising a plurality of processing clusters, each cluster comprising: parallel efficiency analysis circuitry to evaluate different groupings of the first level nodes for a next level of the hierarchical acceleration structure to determine efficiency values for the different groupings; and node merge circuitry to merge the first level nodes based on the efficiency values to form second level nodes.

公开(公告)号：US20200211147A1

公开(公告)日：2020-07-02

申请号：US16236305

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： MICHAEL DOYLE ,  TRAVIS SCHLUESSLER ,  GABOR LIKTOR ,  ATSUO KUWAHARA ,  JEFFERSON AMSTUTZ

IPC: G06T1/20 ,  G06T15/00 ,  G06F16/901 ,  G06F9/38 ,  G06F9/50

Abstract: An apparatus comprising a sorting unit to sort primitives of a graphics image, the primitives to be grouped, each group to form a first level node of a hierarchical acceleration structure; a parallel reconfigurable clustering array to construct the hierarchical acceleration structure, the parallel reconfigurable clustering array comprising a plurality of processing clusters, each cluster comprising: parallel efficiency analysis circuitry to evaluate different groupings of the first level nodes for a next level of the hierarchical acceleration structure to determine efficiency values for the different groupings; and node merge circuitry to merge the first level nodes based on the efficiency values to form second level nodes.

公开(公告)号：US20220327655A1

公开(公告)日：2022-10-13

申请号：US17724299

申请日：2022-04-19

Applicant: Intel Corporation

Inventor： MICHAEL DOYLE ,  TRAVIS SCHLUESSLER ,  GABOR LIKTOR ,  ATSUO KUWAHARA ,  JEFFERSON AMSTUTZ

IPC: G06T1/20 ,  G06F16/901 ,  G06F9/38 ,  G06F9/50 ,  G06T15/00

Abstract: An apparatus comprising a sorting unit to sort primitives of a graphics image, the primitives to be grouped, each group to form a first level node of a hierarchical acceleration structure; a parallel reconfigurable clustering array to construct the hierarchical acceleration structure, the parallel reconfigurable clustering array comprising a plurality of processing clusters, each cluster comprising: parallel efficiency analysis circuitry to evaluate different groupings of the first level nodes for a next level of the hierarchical acceleration structure to determine efficiency values for the different groupings; and node merge circuitry to merge the first level nodes based on the efficiency values to form second level nodes.

公开(公告)号：US20230421738A1

公开(公告)日：2023-12-28

申请号：US18347278

申请日：2023-07-05

Applicant: Intel Corporation

Inventor： MAYURESH VARERKAR ,  STANLEY BARAN ,  MICHAEL APODACA ,  PRASOONKUMAR SURTI ,  ATSUO KUWAHARA ,  NARAYAN BISWAL ,  JILL BOYCE ,  YI-JEN CHIU ,  GOKCEN CILINGIR ,  BARNAN DAS ,  ATUL DIVEKAR ,  SRIKANTH POTLURI ,  NILESH SHAH ,  ARCHIE SHARMA

IPC: H04N13/111 ,  H04N19/597 ,  G06F9/38 ,  G06F3/01 ,  G06N20/00

CPC classification number: H04N13/111 ,  H04N19/597 ,  G06F9/3877 ,  G06F3/012 ,  G06N20/00

Abstract: A mechanism is described for facilitating adaptive resolution and viewpoint-prediction for immersive media in computing environments. An apparatus of embodiments, as described herein, includes one or more processors to receive viewing positions associated with a user with respect to a display, and analyze relevance of media contents based on the viewing positions, where the media content includes immersive videos of scenes captured by one or more cameras. The one or more processors are further to predict portions of the media contents as relevant portions based on the viewing positions and transmit the relevant portions to be rendered and displayed.

公开(公告)号：US20200043217A1

公开(公告)日：2020-02-06

申请号：US16050375

申请日：2018-07-31

Applicant: Intel Corporation

Inventor： GOKCEN CILINGIR ,  ATSUO KUWAHARA ,  NARAYAN BISWAL ,  JAMES HOLLAND ,  SANG-HEE LEE ,  JASON TANNER ,  MAYURESH VARERKAR ,  KAI XIAO

IPC: G06T15/00 ,  G06T9/00 ,  H04N19/597

Abstract: A mechanism is described for facilitating enhanced immersive media pipeline for correction of artifacts and clarity of objects in computing environments. An apparatus of embodiments, as described herein, includes one or more processors to extract semantic data relating to objects in a scene captured through one or more cameras, where the objects include distortions, and form, based on the semantic data, a three-dimensional (3D) model of contents of the scene, where the contents include the objects. The one or more processors are further to encode the 3D model including the contents and the semantic data into an encoded file having encoded contents and encoded semantic data and transmit the encoded file over an immersive media pipeline to facilitate correction of the distortions and rendering the scene including the objects without the distortions.

公开(公告)号：US20220182592A1

公开(公告)日：2022-06-09

申请号：US17526633

申请日：2021-11-15

Applicant: Intel Corporation

Inventor： MAYURESH VARERKAR ,  STANLEY BARAN ,  MICHAEL APODACA ,  PRASOONKUMAR SURTI ,  ATSUO KUWAHARA ,  NARAYAN BISWAL ,  JILL BOYCE ,  YI-JEN CHIU ,  GOKCEN CILINGIR ,  BARNAN DAS ,  ATUL DIVEKAR ,  SRIKANTH POTLURI ,  NILESH SHAH ,  ARCHIE SHARMA

IPC: H04N13/111 ,  H04N19/597 ,  G06F9/38 ,  G06F3/01 ,  G06N20/00

Abstract: A mechanism is described for facilitating adaptive resolution and viewpoint-prediction for immersive media in computing environments. An apparatus of embodiments, as described herein, includes one or more processors to receive viewing positions associated with a user with respect to a display, and analyze relevance of media contents based on the viewing positions, where the media content includes immersive videos of scenes captured by one or more cameras. The one or more processors are further to predict portions of the media contents as relevant portions based on the viewing positions and transmit the relevant portions to be rendered and displayed.

公开(公告)号：US20200211253A1

公开(公告)日：2020-07-02

申请号：US16236176

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： GABOR LIKTOR ,  KARTHIK VAIDYANATHAN ,  JEFFERSON AMSTUTZ ,  ATSUO KUWAHARA ,  MICHAEL DOYLE ,  TRAVIS SCHLUESSLER

IPC: G06T15/00 ,  G06T15/06 ,  G06T1/60

Abstract: Apparatus and method for speculative execution of hit and intersection shaders on programmable ray tracing architectures. For example, one embodiment of an apparatus comprises: single-instruction multiple-data (SIMD) or single-instruction multiple-thread (SIMT) execution units (EUs) to execute shaders; and ray tracing circuitry to execute a ray traversal thread, the ray tracing engine comprising: traversal/intersection circuitry, responsive to the traversal thread, to traverse a ray through an acceleration data structure comprising a plurality of hierarchically arranged nodes and to intersect the ray with a primitive contained within at least one of the nodes; and shader deferral circuitry to defer and aggregate multiple shader invocations resulting from the traversal thread until a particular triggering event is detected, wherein the multiple shaders are to be dispatched on the EUs in a single shader batch upon detection of the triggering event.

公开(公告)号：US20200043122A1

公开(公告)日：2020-02-06

申请号：US16050595

申请日：2018-07-31

Applicant: Intel Corporation

Inventor： KAI XIAO ,  GOKCEN CILINGIR ,  JASON TANNER ,  SANG-HEE LEE ,  ATSUO KUWAHARA

IPC: G06T1/20 ,  G06T15/00 ,  G06T15/80 ,  G06F17/18

Abstract: Embodiments described herein provide an apparatus comprising a processor to divide a first projection into a plurality of regions, the plurality of regions comprising a plurality of pixels, detect errant visual content in a first region in the plurality of regions, determine a detail frequency rating for the first region, and apply one of a first rendering technique to the first region in the plurality of regions when the detail frequency rating for the first region in the plurality of regions fails to meet a detail frequency threshold or a second rendering technique to the first region in the plurality of regions when the detail frequency rating for the first region in the plurality of regions meets a detail frequency threshold. Other embodiments may be described and claimed.