公开(公告)号：US11587851B2

公开(公告)日：2023-02-21

申请号：US17323840

申请日：2021-05-18

Applicant: Intel Corporation

Inventor： Aditya S. Vaidya ,  Ravindranath V. Mahajan ,  Digvijay A. Raorane ,  Paul R. Start

IPC: H01L23/48 ,  H01L23/49 ,  H01L21/76 ,  H01L21/768 ,  H01L23/498 ,  H01L23/00 ,  H01L25/16 ,  H01L23/538 ,  H01L25/065

Abstract: An integrated circuit (IC) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. The bridge die comprises a plurality of vias extending from a first side to a second side of the-bridge die. The-bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. The plurality of vias interconnect ones of the first plurality of pads to ones of the second plurality of pads. The bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.

公开(公告)号：US11049798B2

公开(公告)日：2021-06-29

申请号：US16457336

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Aditya S. Vaidya ,  Ravindranath V. Mahajan ,  Digvijay A. Raorane ,  Paul R. Start

IPC: H01L23/48 ,  H01L23/49 ,  H01L21/76 ,  H01L21/768 ,  H01L23/498 ,  H01L23/00 ,  H01L25/16 ,  H01L23/538 ,  H01L25/065

Abstract: An integrated circuit (IC) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. The bridge die comprises a plurality of vias extending from a first side to a second side of the-bridge die. The-bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. The plurality of vias interconnect snes of the first plurality of pads to ones of the second plurality of pads. The bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.

公开(公告)号：US20190006264A1

公开(公告)日：2019-01-03

申请号：US15640406

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Aditya S. Vaidya ,  Ravindranath V. Mahajan ,  Digvijay A. Raorane ,  Paul R. Start

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/498 ,  H01L23/00 ,  H01L25/16

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/09 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/16 ,  H01L2224/16225

Abstract: An apparatus comprising: a substrate having a first side opposing a second side, and comprises a first conductive layer disposed on the first side of the package substrate, and a second conductive layer disposed between the first side and the second side of the package substrate, the substrate having dielectric material disposed between the first conductive layer and the second conductive layer; and at least one at least one bridge die disposed within the substrate, the at least one bridge die having a first side opposing a second side, and comprising a plurality of vias extending from the first side to the second side of the at least one bridge die, wherein the second conductive layer disposed between the first and second sides of the substrate is coupled to the plurality of vias extending from the first side of the at least one bridge die to the second side of the at least one bridge die.

公开(公告)号：US10672626B2

公开(公告)日：2020-06-02

申请号：US15469284

申请日：2017-03-24

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Aditya S. Vaidya ,  Nachiket R. Raravikar ,  Eric J. Li

IPC: H01L21/56 ,  H01L21/768 ,  H01L21/78 ,  H01L23/498 ,  H01L25/10 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31

Abstract: Embodiments describe a semiconductor package that includes a substrate, a die bonded to the substrate, and a solder paste overmold layer formed over a top surface of the die. In an embodiment, the solder paste comprises a high-melting point metal, a solder matrix, intermetallic compounds and a polymer. The overmold layer has a high elastic modulus, a coefficient of thermal expansion similar to the substrate, and reduces the warpage of the package. In an embodiment, interconnects of a semiconductor package are formed with a no-slump solder paste that includes vents. Vents may be formed through a conductive network formed by the high-melting point metal, solder matrix and intermetallic compounds. In an embodiment, vents provide a path through the interconnect that allows for moisture outgassing. In an embodiment, a mold layer may be mechanically anchored to the interconnects by the vents, thereby providing improved mechanical continuity to the mold layer.

公开(公告)号：US10373893B2

公开(公告)日：2019-08-06

申请号：US15640406

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Aditya S. Vaidya ,  Ravindranath V. Mahajan ,  Digvijay A. Raorane ,  Paul R. Start

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/498 ,  H01L23/00 ,  H01L25/16

Abstract: An integrated circuit (IC) package including a substrate comprising a dielectric, and at least one bridge die embedded in the first dielectric. The embedded bridge die comprises a plurality of through-vias extending from a first side to a second side and a first plurality of pads on the first side and a second plurality of pads on the second side. The first plurality of pads are interconnected to the second plurality of pads by the plurality of through-vias extending vertically through the bridge die. The second plurality of pads is coupled to a buried conductive layer in the substrate by solder joints or by an adhesive conductive film between the second plurality of pads of the bridge die and conductive structures in the buried conductive layer, and wherein the adhesive conductive film is over a second dielectric layer on the bridge die.

公开(公告)号：US12159813B2

公开(公告)日：2024-12-03

申请号：US18111329

申请日：2023-02-17

Applicant: Intel Corporation

Inventor： Aditya S. Vaidya ,  Ravindranath V. Mahajan ,  Digvijay A. Raorane ,  Paul R. Start

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/49 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/16

Abstract: An integrated circuit (IC) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. The bridge die comprises a plurality of vias extending from a first side to a second side of the bridge die. The bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. The plurality of vias interconnect ones of the first plurality of pads to ones of the second plurality of pads. The bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.

公开(公告)号：US20190326198A1

公开(公告)日：2019-10-24

申请号：US16457336

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Aditya S. Vaidya ,  Ravindranath V. Mahajan ,  Digvijay A. Raorane ,  Paul R. Start

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/16 ,  H01L21/768 ,  H01L23/498

Abstract: An integrated circuit (IC) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. The bridge die comprises a plurality of vias extending from a first side to a second side of the-bridge die. The-bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. The plurality of vias interconnect snes of the first plurality of pads to ones of the second plurality of pads. The bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.