公开(公告)号：US12094822B2

公开(公告)日：2024-09-17

申请号：US16950240

申请日：2020-11-17

Applicant: Intel Corporation

Inventor： Guillaume Bouche ,  Andy Chih-Hung Wei ,  Changyok Park

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/522 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L23/5286 ,  H01L21/76897 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/66795 ,  H01L29/785

Abstract: Transistor arrangements fabricated by forming a metal gate cut as an opening that is non-selective to the gate sidewalls are disclosed. The etch process may be used to provide a power rail if the opening is at least partially filled with an electrically conductive material. Once an electrically conductive material has been deposited within the opening to form a power rail, recessing such a material in portions of the power rail that face gate stacks of various transistors may provide further improvements in terms of reduced parasitic capacitance. A mask for a trench contact to be used to electrically couple the power rail to a S/D region of a transistor may be used as a mask when the electrically conductive material of the power rail is recessed to realize a via that is self-aligned to the trench contact.

公开(公告)号：US20240128023A1

公开(公告)日：2024-04-18

申请号：US18396922

申请日：2023-12-27

Applicant: Intel Corporation

Inventor： Changyok Park

IPC: H01G4/35 ,  H01L23/522 ,  H01L27/08

CPC classification number: H01G4/35 ,  H01L23/5223 ,  H01L23/5226 ,  H01L27/0805 ,  H01L28/60

Abstract: Disclosed herein are IC structures with one or more decoupling capacitors based on dummy TSVs provided in a support structure. An example decoupling capacitor includes first and second capacitor electrodes and a capacitor insulator between them. The first capacitor electrode is a liner of a first electrically conductive material on sidewalls and a bottom of an opening in the support structure, the opening in the support structure extending from the first side towards, but not reaching, the second side. The capacitor insulator is a liner of a dielectric material on sidewalls and a bottom of the opening in the support structure lined with the first electrically conductive material. The second capacitor electrode is a second electrically conductive material filling at least a portion of the opening in the support structure lined with the first electrically conductive material and with the dielectric material.

公开(公告)号：US11923150B2

公开(公告)日：2024-03-05

申请号：US16884094

申请日：2020-05-27

Applicant: Intel Corporation

Inventor： Changyok Park

IPC: H01G4/35 ,  H01L23/522 ,  H01L27/08 ,  H01L49/02

CPC classification number: H01G4/35 ,  H01L23/5223 ,  H01L23/5226 ,  H01L27/0805 ,  H01L28/60

Abstract: Disclosed herein are IC structures with one or more decoupling capacitors based on dummy TSVs provided in a support structure. An example decoupling capacitor includes first and second capacitor electrodes and a capacitor insulator between them. The first capacitor electrode is a liner of a first electrically conductive material on sidewalls and a bottom of an opening in the support structure, the opening in the support structure extending from the first side towards, but not reaching, the second side. The capacitor insulator is a liner of a dielectric material on sidewalls and a bottom of the opening in the support structure lined with the first electrically conductive material. The second capacitor electrode is a second electrically conductive material filling at least a portion of the opening in the support structure lined with the first electrically conductive material and with the dielectric material.

公开(公告)号：US20220157722A1

公开(公告)日：2022-05-19

申请号：US16950240

申请日：2020-11-17

Applicant: Intel Corporation

Inventor： Guillaume Bouche ,  Andy Chih-Hung Wei ,  Changyok Park

IPC: H01L23/528 ,  H01L29/78 ,  H01L29/66 ,  H01L23/522 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/768 ,  H01L29/06

Abstract: Transistor arrangements fabricated by forming a metal gate cut as an opening that is non-selective to the gate sidewalls are disclosed. The etch process may be used to provide a power rail if the opening is at least partially filled with an electrically conductive material. Once an electrically conductive material has been deposited within the opening to form a power rail, recessing such a material in portions of the power rail that face gate stacks of various transistors may provide further improvements in terms of reduced parasitic capacitance. A mask for a trench contact to be used to electrically couple the power rail to a S/D region of a transistor may be used as a mask when the electrically conductive material of the power rail is recessed to realize a via that is self-aligned to the trench contact.

公开(公告)号：US20220254872A1

公开(公告)日：2022-08-11

申请号：US17170951

申请日：2021-02-09

Applicant: Intel Corporation

Inventor： Changyok Park

IPC: H01L49/02 ,  H01G4/30 ,  H01G4/012 ,  H01L23/48 ,  H01L21/768

Abstract: Disclosed herein are IC structures with decoupling capacitors based on dummy TSV plates provided in a support structure (e.g., a substrate, a die, a wafer, or a chip). An example decoupling capacitor includes first and second capacitor plates and a capacitor insulator between them. Each capacitor plate is a different blind, plate-like opening in the support structure, the openings at least partially filled with one or more conductive materials. The capacitor plate openings are referred to herein as “dummy TSV plates” because they may be fabricated while providing regular TSV openings in the support structure. Such decoupling capacitors may be better suited for high-speed microprocessor applications than conventional off-chip decoupling capacitors and may advantageously allow integrating on-chip decoupling capacitors with an ample amount of capacitive decoupling, limited or no additional processing steps on top of regular TSV processing, and in areas that may not have been used otherwise.

公开(公告)号：US20220190129A1

公开(公告)日：2022-06-16

申请号：US17123828

申请日：2020-12-16

Applicant: Intel Corporation

Inventor： Andy Chih-Hung Wei ,  Changyok Park ,  Guillaume Bouche ,  Hyuk Ju Ryu ,  Charles Henry Wallace ,  Mohit K. Haran

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/10

Abstract: Disclosed herein are transistor arrangements with trench contacts that have two parts—a first trench contact and a second trench contact—stacked over one another. Such transistor arrangements may be fabricated by forming a first trench contact over a source or drain contact of a transistor, recessing the first trench contact, forming the second trench contact over the first trench contact, and, finally, forming a gate contact that is electrically isolated from, while being self-aligned to, the second trench contact. Such a fabrication process may provide improvements in terms of increased edge placement error margin, cost-efficiency, and device performance, compared to conventional approaches to forming trench and gate contacts. The conductive material of the first trench contact may also be deposited over the gate electrodes of transistors, forming a gate strap, to advantageously reduce gate resistance.

公开(公告)号：US12237388B2

公开(公告)日：2025-02-25

申请号：US17123828

申请日：2020-12-16

Applicant: Intel Corporation

Inventor： Andy Chih-Hung Wei ,  Changyok Park ,  Guillaume Bouche ,  Hyuk Ju Ryu ,  Charles Henry Wallace ,  Mohit K. Haran

IPC: H01L29/423 ,  H01L21/768 ,  H01L25/065 ,  H01L27/088 ,  H01L29/10 ,  H01L29/78

Abstract: Disclosed herein are transistor arrangements with trench contacts that have two parts—a first trench contact and a second trench contact—stacked over one another. Such transistor arrangements may be fabricated by forming a first trench contact over a source or drain contact of a transistor, recessing the first trench contact, forming the second trench contact over the first trench contact, and, finally, forming a gate contact that is electrically isolated from, while being self-aligned to, the second trench contact. Such a fabrication process may provide improvements in terms of increased edge placement error margin, cost-efficiency, and device performance, compared to conventional approaches to forming trench and gate contacts. The conductive material of the first trench contact may also be deposited over the gate electrodes of transistors, forming a gate strap, to advantageously reduce gate resistance.

公开(公告)号：US20240429235A1

公开(公告)日：2024-12-26

申请号：US18337697

申请日：2023-06-20

Applicant: Intel Corporation

Inventor： Bilal Chehab ,  Changyok Park ,  Tuhin Guha Neogi ,  George Joseph Sacks ,  Christophe Berteau-Pavy

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/778 ,  H01L29/786

Abstract: A CFET may include two or more transistors stacked over each other. A transistor may be a FET including a forked semiconductor structure. The source region and drain region of a transistor may have a forked shape including a body and one or more branches protruding from the body. A branch may include a fin, nanoribbon, etc. The channel region may be between a branch of the source region and a branch of the drain region. The body of the source region and the body of the drain region may be on opposite sides of the channel region in two perpendicular directions. The two bodies may be diagonally arranged with respect to the channel region. The body of the source region or drain region may be over a contact that is electrically coupled to a frontside metal layer or a backside metal layer for signal transmission or power delivery.

公开(公告)号：US20210375551A1

公开(公告)日：2021-12-02

申请号：US16884094

申请日：2020-05-27

Applicant: Intel Corporation

Inventor： Changyok Park

IPC: H01G4/35 ,  H01L49/02 ,  H01L23/522 ,  H01L27/08

Abstract: Disclosed herein are IC structures with one or more decoupling capacitors based on dummy TSVs provided in a support structure. An example decoupling capacitor includes first and second capacitor electrodes and a capacitor insulator between them. The first capacitor electrode is a liner of a first electrically conductive material on sidewalls and a bottom of an opening in the support structure, the opening in the support structure extending from the second side towards, but not reaching, the second side. The capacitor insulator is a liner of a dielectric material on sidewalls and a bottom of the opening in the support structure lined with the first electrically conductive material. The second capacitor electrode is a second electrically conductive material filling at least a portion of the opening in the support structure lined with the first electrically conductive material and with the dielectric material.