公开(公告)号：US11145732B2

公开(公告)日：2021-10-12

申请号：US16699566

申请日：2019-11-30

申请人： Intel Corporation

发明人： Ayan Kar ,  Kalyan C. Kolluru ,  Nicholas A. Thomson ,  Mark Armstrong ,  Sameer Jayanta Joglekar ,  Rui Ma ,  Sayan Saha ,  Hyuk Ju Ryu ,  Akm A. Ahsan

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L27/02 ,  H01L29/40 ,  H01L29/08

摘要： Disclosed herein are transistor arrangements of field-effect transistors with dual thickness gate dielectrics. An example transistor arrangement includes a semiconductor channel material, a source region and a drain region, provided in the semiconductor material, and a gate stack provided over a portion of the semiconductor material that is between the source region and the drain region. The gate stack has a thinner gate dielectric in a portion that is closer to the source region and a thicker gate dielectric in a portion that is closer to the drain region, which may effectively realize tunable ballast resistance integrated with the transistor arrangement and may help increase the breakdown voltage and/or decrease the gate leakage of the transistor.

公开(公告)号：US20230317408A1

公开(公告)日：2023-10-05

申请号：US17711785

申请日：2022-04-01

申请人： Intel Corporation

发明人： Xianghong Tong ,  Martin Von Haartman ,  Wen-Hsien Chuang ,  Zhiyong Ma ,  Hyuk Ju Ryu ,  Prasoon Joshi ,  May Ling Oh ,  Jennifer Huening ,  Shuai Zhao ,  Charles Peterson ,  Ira Jewell ,  Hasan Faraby

IPC分类号： H01J37/26 ,  H01J37/28 ,  H01J37/244

CPC分类号： H01J37/265 ,  H01J37/28 ,  H01J37/244 ,  H01J2237/2443 ,  H01J2237/2814 ,  H01J2237/2801 ,  H01J2237/221

摘要： Pulsed beam prober systems, devices, and techniques are described herein related to providing a beam detection frequency that is less than a electrical test frequency. An electrical test signal at the electrical test frequency is provided to die under test. A pulsed beam is applied to the die such that the pulsed beam has packets of beam pulses or a frequency delta with respect to the electrical test frequency. The packets of beam pulses or the frequency delta elicits a detectable beam modulation in an imaging signal reflected from the die such that the imaging signal is modulated at a detection frequency less than the electrical test frequency.

公开(公告)号：US20230305057A1

公开(公告)日：2023-09-28

申请号：US17701323

申请日：2022-03-22

申请人： Intel Corporation

发明人： Xianghong Tong ,  Martin Von Haartman ,  Zhiyong Ma ,  Jennifer J. Huening ,  Hyuk Ju Ryu ,  Christopher Morgan ,  Shuai Zhao ,  Ramune Nagisetty ,  Tuyen K. Tran ,  Wen-Hsien Chuang

IPC分类号： G01R31/307 ,  G01R1/073

CPC分类号： G01R31/307 ,  G01R1/07342

摘要： Wafer level electron beam prober systems, devices, and techniques, are described herein related to providing wafer level testing for fabricated device structures. Such wafer level testing contacts a first side of a die of a wafer with a probe to provide test signals to the die under test and performs e-beam imaging of the first side of the die while the test signals are provided to the die under test.

公开(公告)号：US20220190129A1

公开(公告)日：2022-06-16

申请号：US17123828

申请日：2020-12-16

申请人： Intel Corporation

发明人： Andy Chih-Hung Wei ,  Changyok Park ,  Guillaume Bouche ,  Hyuk Ju Ryu ,  Charles Henry Wallace ,  Mohit K. Haran

IPC分类号： H01L29/423 ,  H01L29/78 ,  H01L29/10

摘要： Disclosed herein are transistor arrangements with trench contacts that have two parts—a first trench contact and a second trench contact—stacked over one another. Such transistor arrangements may be fabricated by forming a first trench contact over a source or drain contact of a transistor, recessing the first trench contact, forming the second trench contact over the first trench contact, and, finally, forming a gate contact that is electrically isolated from, while being self-aligned to, the second trench contact. Such a fabrication process may provide improvements in terms of increased edge placement error margin, cost-efficiency, and device performance, compared to conventional approaches to forming trench and gate contacts. The conductive material of the first trench contact may also be deposited over the gate electrodes of transistors, forming a gate strap, to advantageously reduce gate resistance.

公开(公告)号：US20210167180A1

公开(公告)日：2021-06-03

申请号：US16699566

申请日：2019-11-30

申请人： Intel Corporation

发明人： Ayan Kar ,  Kalyan C. Kolluru ,  Nicholas A. Thomson ,  Mark Armstrong ,  Sameer Jayanta Joglekar ,  Rui Ma ,  Sayan Saha ,  Hyuk Ju Ryu ,  Akm A. Ahsan

IPC分类号： H01L29/423 ,  H01L27/02 ,  H01L29/78 ,  H01L29/08 ,  H01L29/40

摘要： Disclosed herein are transistor arrangements of field-effect transistors with dual thickness gate dielectrics. An example transistor arrangement includes a semiconductor channel material, a source region and a drain region, provided in the semiconductor material, and a gate stack provided over a portion of the semiconductor material that is between the source region and the drain region. The gate stack has a thinner gate dielectric in a portion that is closer to the source region and a thicker gate dielectric in a portion that is closer to the drain region, which may effectively realize tunable ballast resistance integrated with the transistor arrangement and may help increase the breakdown voltage and/or decrease the gate leakage of the transistor.