公开(公告)号：US20160180958A1

公开(公告)日：2016-06-23

申请号：US14579971

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： SHYAM SUNDER RAGHUNATHAN ,  IWEN CHAO ,  XIN GUO ,  PRANAV KALAVADE ,  KRISHNA K. PARAT ,  FENG ZHU

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/32 ,  G11C16/14

CPC classification number: G06F12/0246 ,  G06F11/1084 ,  G06F2212/7211 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/32 ,  G11C16/349 ,  G11C16/3495 ,  G11C29/021 ,  G11C29/028

Abstract: Apparatus, systems, and methods to implement dynamic memory management in nonvolatile memory devices are described. In one example, a controller comprises logic to monitor at least one performance parameter of a nonvolatile memory, determine when the at least one performance parameter passes a threshold which indicates a degradation in performance for the nonvolatile memory, and in response to the at least one performance parameter passing the threshold, to modify at least one operational attribute of the nonvolatile memory. Other examples are also disclosed and claimed.

Abstract translation: 描述了在非易失性存储器件中实现动态存储器管理的装置，系统和方法。 在一个示例中，控制器包括用于监视非易失性存储器的至少一个性能参数的逻辑，确定何时至少一个性能参数通过指示非易失性存储器性能下降的阈值，以及响应于该至少一个 性能参数通过阈值，以修改非易失性存储器的至少一个操作属性。 还公开并要求保护其他实例。

公开(公告)号：US20180189154A1

公开(公告)日：2018-07-05

申请号：US15394261

申请日：2016-12-29

Applicant: INTEL CORPORATION

Inventor： FENG ZHU ,  ALIASGAR S. MADRASWALA ,  XIN GUO

IPC: G06F11/20 ,  G06F3/06 ,  G11C7/14

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G11C7/14 ,  G11C29/00 ,  G11C29/52

Abstract: Examples herein include techniques for flash page retirement following one or more defects in nonvolatile memory. In some examples, a storage controller may retire a first logical page in response to a first read error, and write data to the one or more NMV devices in a program-erase (P/E) cycle without a dummy page being programmed or generated for the retired first logical page. The storage controller may further retire a second logical page in response to a second read error, wherein the first logical page has a higher order than the second logical page in a same physical memory page.