公开(公告)号：US11301325B2

公开(公告)日：2022-04-12

申请号：US16888449

申请日：2020-05-29

Applicant: Intel Corporation

Inventor： Siddhartha Chhabra ,  Ronald Perez ,  Hsing-Min Chen ,  Manjula Peddireddy

IPC: G06F11/10 ,  H04L9/32

Abstract: A write request causes controller circuitry to write an encrypted data line and First Tier metadata portion including MAC data and a first portion of ECC data to a first memory circuitry portion and a second portion of ECC data to a sequestered, second memory circuitry portion. A read request causes the controller circuitry to read the encrypted data line and the First Tier metadata portion from the first memory circuitry portion. Using the first portion of the ECC data in the First Tier metadata portion, the controller circuitry determines if an error exists in the encrypted data line. If no error is detected, the controller circuitry decrypts and verifies the data line using the MAC data in the First Tier metadata portion. If an error in the data line is detected, the Second Tier metadata portion, is fetched from the sequestered, second memory circuitry portion and the error corrected.

公开(公告)号：US20210374000A1

公开(公告)日：2021-12-02

申请号：US16888449

申请日：2020-05-29

Applicant: Intel Corporation

Inventor： Siddhartha Chhabra ,  Ronald Perez ,  Hsing-Min Chen ,  Manjula Peddireddy

IPC: G06F11/10 ,  H04L9/32

Abstract: A write request causes controller circuitry to write an encrypted data line and First Tier metadata portion including MAC data and a first portion of ECC data to a first memory circuitry portion and a second portion of ECC data to a sequestered, second memory circuitry portion. A read request causes the controller circuitry to read the encrypted data line and the First Tier metadata portion from the first memory circuitry portion. Using the first portion of the ECC data included in the First Tier metadata portion, the controller circuitry determines if an error exists in the encrypted data line. If no error is detected, the controller circuitry decrypts and verifies the data line using the MAC data included in the First Tier metadata portion. If an error in the data line is detected by the controller circuitry, the Second Tier metadata portion, containing the second portion of the ECC data is fetched from the sequestered, second memory circuitry portion and the error corrected.

公开(公告)号：US20220222143A1

公开(公告)日：2022-07-14

申请号：US17708984

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Siddhartha Chhabra ,  Ronald Perez ,  Hsing-Min Chen ,  Manjula Peddireddy

IPC: G06F11/10 ,  H04L9/32

Abstract: A write request causes controller circuitry to write an encrypted data line and First Tier metadata portion including MAC data and a first portion of ECC data to a first memory circuitry portion and a second portion of ECC data to a sequestered, second memory circuitry portion. A read request causes the controller circuitry to read the encrypted data line and the First Tier metadata portion from the first memory circuitry portion. Using the first portion of the ECC data included in the First Tier metadata portion, the controller circuitry determines if an error exists in the encrypted data line. If no error is detected, the controller circuitry decrypts and verifies the data line using the MAC data included in the First Tier metadata portion. If an error in the data line is detected by the controller circuitry, the Second Tier metadata portion, containing the second portion of the ECC data is fetched from the sequestered, second memory circuitry portion and the error corrected.

公开(公告)号：US12235720B2

公开(公告)日：2025-02-25

申请号：US18268956

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Rajat Agarwal ,  Hsing-Min Chen ,  Wei P. Chen ,  Wei Wu ,  Jing Ling ,  Kuljit S. Bains ,  Kjersten E. Criss ,  Deep K. Buch ,  Theodros Yigzaw ,  John G. Holm ,  Andrew M. Rudoff ,  Vaibhav Singh ,  Sreenivas Mandava

IPC: G06F11/10

Abstract: A memory subsystem includes memory devices with space dynamically allocated for improvement of reliability, availability, and serviceability (RAS) in the system. Error checking and correction (ECC) logic detects an error in all or a portion of a memory device. In response to error detection, the system can dynamically perform one or more of: allocate active memory device space for sparing to spare a failed memory segment; write a poison pattern into a failed cacheline to mark it as failed; perform permanent fault detection (PFD) and adjust application of ECC based on PFD detection; or, spare only a portion of a device and leave another portion active, including adjusting ECC based on the spared portion. The error detection can be based on bits of an ECC device, and error correction based on those bits and additional bits stored on the data devices.

公开(公告)号：US20220334736A1

公开(公告)日：2022-10-20

申请号：US17856637

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Hsing-Min Chen ,  Theodros Yigzaw ,  Russell Clapp ,  Saravanan Sethuraman ,  Patricia Mwove Shaffer

IPC: G06F3/06

Abstract: An embodiment of an electronic apparatus may comprise one or more substrates and a controller coupled to the one or more substrates, the controller including circuitry to apply a reliability, availability, and serviceability (RAS) policy for access to a memory in accordance with a first RAS scheme, change the applied RAS policy in accordance with a second RAS scheme at runtime, where the second RAS scheme is different from the first RAS scheme, and access the memory in accordance with the applied RAS policy. Other embodiments are disclosed and claimed.