公开(公告)号：US11301325B2

公开(公告)日：2022-04-12

申请号：US16888449

申请日：2020-05-29

Applicant: Intel Corporation

Inventor： Siddhartha Chhabra ,  Ronald Perez ,  Hsing-Min Chen ,  Manjula Peddireddy

IPC: G06F11/10 ,  H04L9/32

Abstract: A write request causes controller circuitry to write an encrypted data line and First Tier metadata portion including MAC data and a first portion of ECC data to a first memory circuitry portion and a second portion of ECC data to a sequestered, second memory circuitry portion. A read request causes the controller circuitry to read the encrypted data line and the First Tier metadata portion from the first memory circuitry portion. Using the first portion of the ECC data in the First Tier metadata portion, the controller circuitry determines if an error exists in the encrypted data line. If no error is detected, the controller circuitry decrypts and verifies the data line using the MAC data in the First Tier metadata portion. If an error in the data line is detected, the Second Tier metadata portion, is fetched from the sequestered, second memory circuitry portion and the error corrected.

公开(公告)号：US20210374000A1

公开(公告)日：2021-12-02

申请号：US16888449

申请日：2020-05-29

Applicant: Intel Corporation

Inventor： Siddhartha Chhabra ,  Ronald Perez ,  Hsing-Min Chen ,  Manjula Peddireddy

IPC: G06F11/10 ,  H04L9/32

Abstract: A write request causes controller circuitry to write an encrypted data line and First Tier metadata portion including MAC data and a first portion of ECC data to a first memory circuitry portion and a second portion of ECC data to a sequestered, second memory circuitry portion. A read request causes the controller circuitry to read the encrypted data line and the First Tier metadata portion from the first memory circuitry portion. Using the first portion of the ECC data included in the First Tier metadata portion, the controller circuitry determines if an error exists in the encrypted data line. If no error is detected, the controller circuitry decrypts and verifies the data line using the MAC data included in the First Tier metadata portion. If an error in the data line is detected by the controller circuitry, the Second Tier metadata portion, containing the second portion of the ECC data is fetched from the sequestered, second memory circuitry portion and the error corrected.

公开(公告)号：US12143501B2

公开(公告)日：2024-11-12

申请号：US17134352

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Siddhartha Chhabra ,  Manjula Peddireddy ,  Hormuzd Khosravi

IPC: H04L9/08 ,  G06F12/14 ,  G06F13/16 ,  G06F21/64 ,  G06F21/78 ,  H04L9/32 ,  H04L9/40 ,  G06F21/72 ,  G06F21/79

Abstract: In embodiments detailed herein describe an encryption architecture with fast zero support (e.g., FZ-MKTME) to allow memory encryption and integrity architecture to work efficiently with 3DXP or other far memory memories. In particular, an encryption engine for the purpose of fast zeroing in the far memory controller is detailed along with mechanisms for consistent key programming of this engine. For example, an instruction is detailed which allows software to send keys protected even when the controller is located outside of a system on a chip (SoC), etc.

公开(公告)号：US20250103397A1

公开(公告)日：2025-03-27

申请号：US18401399

申请日：2023-12-30

Applicant: Intel Corporation

Inventor： Andrew J. Herdrich ,  Daniel Joe ,  Filip Schmole ,  Philip Abraham ,  Stephen R. Van Doren ,  Priya Autee ,  Rajesh M. Sankaran ,  Anthony Luck ,  Philip Lantz ,  Eric Wehage ,  Edwin Verplanke ,  James Coleman ,  Scott Oehrlein ,  David M. Lee ,  Lee Albion ,  David Harriman ,  Vinit Mathew Abraham ,  Yi-Feng Liu ,  Manjula Peddireddy ,  Robert G. Blankenship

IPC: G06F9/50

Abstract: Techniques for quality of service (QoS) support for input/output devices and other agents are described. In embodiments, a processing device includes execution circuitry to execute a plurality of software threads; hardware to control monitoring or allocating, among the plurality of software threads, one or more shared resources; and configuration storage to enable the monitoring or allocating of the one or more shared resources among the plurality of software threads and one or more channels through which one or more devices are to be connected to the one or more shared resources.

公开(公告)号：US11954047B2

公开(公告)日：2024-04-09

申请号：US17033745

申请日：2020-09-26

Applicant: Intel Corporation

Inventor： Mahesh Natu ,  Anand K. Enamandram ,  Manjula Peddireddy ,  Robert A. Branch ,  Tiffany J. Kasanicky ,  Siddhartha Chhabra ,  Hormuzd Khosravi

IPC: G06F12/14 ,  G06F9/30 ,  G06F12/02

CPC classification number: G06F12/1441 ,  G06F9/30101 ,  G06F9/30145 ,  G06F12/0238 ,  G06F12/1408

Abstract: Systems, methods, and apparatuses to implement spatially unique and location independent persistent memory encryption are described. In one embodiment, a system on a chip (SoC) includes at least one persistent range register to indicate a persistent range of memory, an address modifying circuit to check if an address for a memory store request is within the persistent range indicated by the at least one persistent range register, and append a unique identifier value, for a component corresponding to the memory store request for the address, to the address to generate a modified address and output the modified address as an output address when the address is within the persistent range, and output the address as the output address when the address is not within the persistent range, and an encryption engine circuit to generate a ciphertext based on the output address.

公开(公告)号：US20220222143A1

公开(公告)日：2022-07-14

申请号：US17708984

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Siddhartha Chhabra ,  Ronald Perez ,  Hsing-Min Chen ,  Manjula Peddireddy

IPC: G06F11/10 ,  H04L9/32

Abstract: A write request causes controller circuitry to write an encrypted data line and First Tier metadata portion including MAC data and a first portion of ECC data to a first memory circuitry portion and a second portion of ECC data to a sequestered, second memory circuitry portion. A read request causes the controller circuitry to read the encrypted data line and the First Tier metadata portion from the first memory circuitry portion. Using the first portion of the ECC data included in the First Tier metadata portion, the controller circuitry determines if an error exists in the encrypted data line. If no error is detected, the controller circuitry decrypts and verifies the data line using the MAC data included in the First Tier metadata portion. If an error in the data line is detected by the controller circuitry, the Second Tier metadata portion, containing the second portion of the ECC data is fetched from the sequestered, second memory circuitry portion and the error corrected.