中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

25 records (took 0.02 seconds)

    Adaptive time-to-digital converter and method
    3.
    发明授权
    Adaptive time-to-digital converter and method 有权

    公开(公告)号：US10474110B1

    公开(公告)日：2019-11-12

    申请号：US16229638

    申请日：2018-12-21

    Applicant: Intel Corporation

    Inventor： Gil Horovitz ,  Aryeh Farber ,  Nisim Machluf ,  Evgeny Shumaker ,  Igal Kushnir

    IPC: G04F10/00 ,  H03L7/083 ,  H03L7/095 ,  H03L7/08

    Abstract: Systems, methods, and circuitries are disclosed for controlling an adaptive time-to-digital converter (TDC) that determines a phase difference between a reference signal and a phase locked loop (PLL) feedback signal. Adaptive TDC circuitry includes a chain of n delay elements each characterized by an incremental delay. Gate circuitry outputs a gated PLL feedback signal while a gating enable signal has an enable value. N sampling elements, each associated with a delay element, are enabled by the reference signal arriving at the input of the associated delay element to store a value of the gated PLL feedback signal. Adaptive gating circuitry is configured to generate the gating enable signal based on the incremental delay and a period of the PLL feedback signal. A supply voltage for the delay elements may be controlled to cause the delay elements to exhibit a desired incremental delay.

    Concept for a digital controlled loop and a digital loop filter
    5.
    发明授权
    Concept for a digital controlled loop and a digital loop filter 有权

    公开(公告)号：US11558059B2

    公开(公告)日：2023-01-17

    申请号：US17004037

    申请日：2020-08-27

    Applicant: Intel Corporation

    Inventor： Igal Kushnir ,  Evgeny Shumaker ,  Aryeh Farber ,  Gil Horovitz

    IPC: H03L7/099 ,  H03L7/093

    Abstract: Examples relate to a digitally controlled oscillator circuit arrangement, a digitally controlled oscillation means, a method for a digitally controlled oscillator, a digital loop filter circuit arrangement, a digital loop filtering means, a method for a digital loop filter, a phase locked loop circuit arrangement and phase locked loop, a user device and a base station. The digitally controlled oscillator circuit arrangement comprises input circuitry for obtaining a frequency setting signal, the frequency setting signal comprising a plurality of signal components, selection circuitry for selecting one signal component of the plurality of signal components of the frequency setting signal based on an oscillation signal of the digitally controlled oscillator circuit arrangement, wherein the selection circuitry comprises counting circuitry and multiplexing circuitry, signal generation circuitry for generating the oscillation signal based on the selected signal component of the frequency setting signal, and output circuitry for providing the oscillation signal.

    Adaptive time-to-digital converter and method
    8.
    发明授权
    Adaptive time-to-digital converter and method 有权

    公开(公告)号：US10809669B2

    公开(公告)日：2020-10-20

    申请号：US16600794

    申请日：2019-10-14

    Applicant: Intel Corporation

    Inventor： Gil Horovitz ,  Aryeh Farber ,  Nisim Machluf ,  Evgeny Shumaker ,  Igal Kushnir

    IPC: G04F10/00 ,  H03L7/083 ,  H03L7/095 ,  H03L7/08

    Abstract: Systems, methods, and circuitries are disclosed for controlling an adaptive time-to-digital converter (TDC) that determines a phase difference between a reference signal and a phase locked loop (PLL) feedback signal. Adaptive TDC circuitry includes a chain of n delay elements each characterized by a delay. Gate circuitry generates a gated PLL feedback signal while a gating enable signal has an enable value. N sampling elements, each associated with a delay element, are enabled by the reference signal arriving at the input of the associated delay element to store a value of the gated PLL feedback signal. Adaptive gating circuitry is configured to generate the gating enable signal based on the delay and a period of the PLL feedback signal. A supply voltage for the delay elements may be controlled to cause the delay elements to exhibit a desired delay.

    FREQUENCY SYNTHESIS WITH REFERENCE SIGNAL GENERATED BY OPPORTUNISTIC PHASE LOCKED LOOP
    9.
    发明申请
    FREQUENCY SYNTHESIS WITH REFERENCE SIGNAL GENERATED BY OPPORTUNISTIC PHASE LOCKED LOOP 有权

    公开(公告)号：US20210050857A1

    公开(公告)日：2021-02-18

    申请号：US17066490

    申请日：2020-10-09

    Applicant: Intel Corporation

    Inventor： Gil Horovitz ,  Sharon Malevsky ,  Evgeny Shumaker ,  Igal Kushnir

    IPC: H03L7/099 ,  H04B1/00

    Abstract: Systems, methods, and circuitries are provided to generate a radio frequency (RF) signal having a desired radio frequency fRF. In one example a frequency synthesizer system includes a clock, an opportunistic phase locked loop (PLL), and an RF PLL. The clock circuitry is configured to generate a clock signal having a frequency fXTL. The opportunistic phase locked loop (PLL) is configured to generate a reference signal having a reference frequency fREF that is close to a free-running frequency of an oscillator in the opportunistic PLL. The opportunistic PLL is configured to synchronize the reference signal to the clock signal. The RF PLL is configured to generate the RF signal having the desired radio frequency and to synchronize the RF signal with the reference signal.

Patent Agency Ranking