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    Fill pattern to enhance e-beam process margin
    3.
    发明授权
    Fill pattern to enhance e-beam process margin 有权

    公开(公告)号：US11107658B2

    公开(公告)日：2021-08-31

    申请号：US16323128

    申请日：2016-09-30

    Applicant: Intel Corporation

    Inventor： Shakul Tandon ,  Mark C. Phillips ,  Shem O. Ogadhoh ,  John A. Swanson

    IPC: H01J37/317 ,  H01L21/033 ,  H01J37/30 ,  H01L21/027 ,  H01J37/04

    Abstract: Lithographic apparatuses suitable for complementary e-beam lithography (CEBL) are described. In an example, a method of forming a pattern for a semiconductor structure includes forming a pattern of parallel lines above a substrate. The method also includes aligning the substrate in an e-beam tool to provide the pattern of parallel lines parallel with a scan direction of the e-beam tool. The e-beam tool includes a column having a blanker aperture array (BAA) with a staggered pair of columns of openings along an array direction orthogonal to the scan direction. The method also includes forming a pattern of cuts or vias in or above the pattern of parallel lines to provide line breaks for the pattern of parallel lines by scanning the substrate along the scan direction. A cumulative current through the column has a non-zero and substantially uniform cumulative current value throughout the scanning.

    Fill pattern to enhance ebeam process margin
    4.
    发明授权
    Fill pattern to enhance ebeam process margin 有权

    公开(公告)号：US11581162B2

    公开(公告)日：2023-02-14

    申请号：US17388945

    申请日：2021-07-29

    Applicant: Intel Corporation

    Inventor： Shakul Tandon ,  Mark C. Phillips ,  Shem O. Ogadhoh ,  John A. Swanson

    IPC: H01J37/30 ,  H01J37/317 ,  H01L21/027 ,  H01J37/04 ,  H01L21/033

    Abstract: Lithographic apparatuses suitable for complementary e-beam lithography (CEBL) are described. In an example, a method of forming a pattern for a semiconductor structure includes forming a pattern of parallel lines above a substrate. The method also includes aligning the substrate in an e-beam tool to provide the pattern of parallel lines parallel with a scan direction of the e-beam tool. The e-beam tool includes a column having a blanker aperture array (BAA) with a staggered pair of columns of openings along an array direction orthogonal to the scan direction. The method also includes forming a pattern of cuts or vias in or above the pattern of parallel lines to provide line breaks for the pattern of parallel lines by scanning the substrate along the scan direction. A cumulative current through the column has a non-zero and substantially uniform cumulative current value throughout the scanning.

    Fast pattern matching
    5.
    发明授权
    Fast pattern matching 有权

    公开(公告)号：US11010525B2

    公开(公告)日：2021-05-18

    申请号：US16457974

    申请日：2019-06-29

    Applicant: Intel Corporation

    Inventor： Bikram Baidya ,  John A. Swanson ,  Prasad N. Atkar ,  Vivek K. Singh ,  Aswin Sreedhar

    IPC: G06F30/33 ,  G06F30/39

    Abstract: A search engine receives data describing reference geometry and generates a hash based on the reference geometry. A reference bloom filter is generated for the reference geometry based on the hash. The search engine performs a search to determine whether instances of the reference geometry are present in an integrated circuit (IC) layout. The search includes comparing the reference bloom filter with each one of a plurality of bloom filters corresponding to a plurality of subdomains of the IC layout. Based on results of the comparison, one or more subdomains of interest are identified and searched to determine whether the particular reference geometry is present in the subdomain.

    Random forest model for prediction of chip layout attributes
    6.
    发明授权
    Random forest model for prediction of chip layout attributes 有权

    公开(公告)号：US10885259B2

    公开(公告)日：2021-01-05

    申请号：US16557945

    申请日：2019-08-30

    Applicant: Intel Corporation

    Inventor： Bikram Baidya ,  John A. Swanson ,  Kumara Sastry ,  Prasad N. Atkar ,  Vivek K. Singh

    IPC: G06F30/00 ,  G06F30/398 ,  G06F17/18 ,  G06N5/02 ,  G06K9/62 ,  G06F30/392 ,  G06N20/00

    Abstract: An improved random forest model is provided, which has been trained based on silicon data generated from tests of previously fabricated chips. An input is provided to the random forest model, the input including a feature set of a pattern within a particular chip layout, the feature set identifying geometric attributes of polygonal elements within the pattern. A result is generated by the random forest model based on the input, where the result identifies a predicted attribute of the pattern based on the silicon data, and the result is generated based at least in part on determining, within the random forest model, that geometric attributes of the pattern were included in the previously fabricated chips, where the previously fabricated chips have chip layouts are different from the particular chip layout.

    Unsupervised clustering to identify anomalies
    8.
    发明授权
    Unsupervised clustering to identify anomalies 有权

    公开(公告)号：US11282189B2

    公开(公告)日：2022-03-22

    申请号：US16572594

    申请日：2019-09-16

    Applicant: Intel Corporation

    Inventor： John A. Swanson ,  Kenny K. Toh ,  Kumara Sastry ,  Lillian Chang ,  Manuj Swaroop ,  Vivek K. Singh

    IPC: G06T7/00

    Abstract: Images are accessed representing a status in a fabrication of a semiconductor chip corresponding to a particular stage in the fabrication. Distortion is removed from the images and actual features of the semiconductor chip are extracted from the images. Synthesized ideal features of the semiconductor chip associated with completion of the particular stage in the fabrication are determined from the one or more images. The actual features are compared to the ideal features to determine whether anomalies associated with the particular stage exist in the semiconductor chip.

    UNSUPERVISED CLUSTERING TO IDENTIFY ANOMALIES
    9.
    发明申请
    UNSUPERVISED CLUSTERING TO IDENTIFY ANOMALIES 审中-公开

    公开(公告)号：US20200013157A1

    公开(公告)日：2020-01-09

    申请号：US16572594

    申请日：2019-09-16

    Applicant: Intel Corporation

    Inventor： John A. Swanson ,  Kenny K. Toh ,  Kumara Sastry ,  Lillian Chang ,  Manuj Swaroop ,  Vivek K. Singh

    IPC: G06T7/00

    Abstract: Images are accessed representing a status in a fabrication of a semiconductor chip corresponding to a particular stage in the fabrication. Distortion is removed from the images and actual features of the semiconductor chip are extracted from the images. Synthesized ideal features of the semiconductor chip associated with completion of the particular stage in the fabrication are determined from the one or more images. The actual features are compared to the ideal features to determine whether anomalies associated with the particular stage exist in the semiconductor chip

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