公开(公告)号：US11581162B2

公开(公告)日：2023-02-14

申请号：US17388945

申请日：2021-07-29

Applicant: Intel Corporation

Inventor： Shakul Tandon ,  Mark C. Phillips ,  Shem O. Ogadhoh ,  John A. Swanson

IPC: H01J37/30 ,  H01J37/317 ,  H01L21/027 ,  H01J37/04 ,  H01L21/033

Abstract: Lithographic apparatuses suitable for complementary e-beam lithography (CEBL) are described. In an example, a method of forming a pattern for a semiconductor structure includes forming a pattern of parallel lines above a substrate. The method also includes aligning the substrate in an e-beam tool to provide the pattern of parallel lines parallel with a scan direction of the e-beam tool. The e-beam tool includes a column having a blanker aperture array (BAA) with a staggered pair of columns of openings along an array direction orthogonal to the scan direction. The method also includes forming a pattern of cuts or vias in or above the pattern of parallel lines to provide line breaks for the pattern of parallel lines by scanning the substrate along the scan direction. A cumulative current through the column has a non-zero and substantially uniform cumulative current value throughout the scanning.

公开(公告)号：US12080643B2

公开(公告)日：2024-09-03

申请号：US16583691

申请日：2019-09-26

Applicant: Intel Corporation

Inventor： Travis W. Lajoie ,  Abhishek A. Sharma ,  Juan G. Alzate Vinasco ,  Chieh-Jen Ku ,  Shem O. Ogadhoh ,  Allen B. Gardiner ,  Blake C. Lin ,  Yih Wang ,  Pei-Hua Wang ,  Jack T. Kavalieros ,  Bernhard Sell ,  Tahir Ghani

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76829 ,  H01L23/5223 ,  H01L23/5226

Abstract: Integrated circuit structures having differentiated interconnect lines in a same dielectric layer, and methods of fabricating integrated circuit structures having differentiated interconnect lines in a same dielectric layer, are described. In an example, an integrated circuit structure includes an inter-layer dielectric (ILD) layer above a substrate. A plurality of conductive interconnect lines is in the ILD layer. The plurality of conductive interconnect lines includes a first interconnect line having a first height, and a second interconnect line immediately laterally adjacent to but spaced apart from the first interconnect line, the second interconnect line having a second height less than the first height.

公开(公告)号：US11107658B2

公开(公告)日：2021-08-31

申请号：US16323128

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Shakul Tandon ,  Mark C. Phillips ,  Shem O. Ogadhoh ,  John A. Swanson

IPC: H01J37/317 ,  H01L21/033 ,  H01J37/30 ,  H01L21/027 ,  H01J37/04

Abstract: Lithographic apparatuses suitable for complementary e-beam lithography (CEBL) are described. In an example, a method of forming a pattern for a semiconductor structure includes forming a pattern of parallel lines above a substrate. The method also includes aligning the substrate in an e-beam tool to provide the pattern of parallel lines parallel with a scan direction of the e-beam tool. The e-beam tool includes a column having a blanker aperture array (BAA) with a staggered pair of columns of openings along an array direction orthogonal to the scan direction. The method also includes forming a pattern of cuts or vias in or above the pattern of parallel lines to provide line breaks for the pattern of parallel lines by scanning the substrate along the scan direction. A cumulative current through the column has a non-zero and substantially uniform cumulative current value throughout the scanning.

公开(公告)号：US20190305081A1

公开(公告)日：2019-10-03

申请号：US15941557

申请日：2018-03-30

Applicant: INTEL CORPORATION

Inventor： Travis W. LaJoie ,  Abhishek A. Sharma ,  Juan Alzate-Vinasco ,  Chieh-Jen Ku ,  Shem O. Ogadhoh ,  Allen B. Gardiner ,  Blake C. Lin ,  Yih Wang ,  Pei-Hua Wang ,  Jack T. Kavalieros ,  Bernhard Sell ,  Tahir Ghani

IPC: H01L29/06 ,  H01L27/12 ,  H01L21/764 ,  H01L21/02 ,  H01L29/423 ,  H01L27/105

Abstract: An integrated circuit includes a base, a first transistor structure on or above the base, and a second transistor structure on or above the base, where the second transistor structure is spaced from the first transistor structure. An insulator material at least partially encapsulates an airgap or other gas pocket laterally between the first transistor structure and the second transistor structure. The gas pocket is at least 5 nm in height and at least 5 nm wide according to an embodiment, and in some cases is as tall or taller than active device layers of the transistor structures it separates.

公开(公告)号：US09046761B2

公开(公告)日：2015-06-02

申请号：US13846319

申请日：2013-03-18

Applicant: Intel Corporation

Inventor： Shem O. Ogadhoh ,  Charles H. Wallace ,  Ryan Pearman ,  Sven Henrichs ,  Arvind Sundaramurthy ,  Swaminathan Sivakumar

IPC: G03F1/36 ,  G03F1/00 ,  G03F1/26

CPC classification number: G03F1/00 ,  G03F1/26 ,  G03F1/36

Abstract: Techniques are disclosed for using sub-resolution phased assist features (SPAF) in a lithography mask to improve through process pattern fidelity and/or mitigate inverted aerial image problems. The technique also may be used to improve image contrast in non-inverted weak image sites. The use of SPAF in accordance with some such embodiments requires no adjustment to existing design rules, although adjustments can be made to enable compliance with mask inspection constraints. The use of SPAF also does not require changing existing fab or manufacturing processes, especially if such processes already comprehend phased shift mask capabilities. The SPAFs can be used to enhance aerial image contrast, without the SPAFs themselves printing. In addition, the SPAF phase etch depth can be optimized so as to make adjustments to a given predicted printed feature critical dimension.

Abstract translation: 公开了在光刻掩模中使用子分辨率相控辅助特征（SPAF）来改进过程模式保真度和/或减轻倒置的空中图像问题的技术。 该技术也可用于改善非反转弱图像位置中的图像对比度。 根据一些这样的实施例的SPAF的使用不需要调整现有的设计规则，尽管可以进行调整以使得能够符合掩模检查约束。 使用SPAF也不需要更改现有的晶圆厂或制造工艺，特别是如果这些工艺已经了解了相位移位掩模功能。 SPAF可以用于增强空中图像对比度，而不需要SPAF自身的打印。 此外，可以优化SPAF相蚀刻深度，以便对给定的预测印刷特征临界尺寸进行调整。