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公开(公告)号:US09685204B2
公开(公告)日:2017-06-20
申请号:US15189314
申请日:2016-06-22
Applicant: Intel Corporation
Inventor: Mase J Taub , Sandeep K. Guliani , Kiran Pangal
CPC classification number: G11C13/0004 , G11C5/02 , G11C7/00 , G11C13/004 , G11C13/0069 , G11C2013/0076 , G11C2013/0078 , G11C2013/0092 , G11C2213/77
Abstract: A system and technique is disclosed for writing data in a cross-point memory. The state of one or more memory cells of the cross-point memory are sensed and then are continued to be selected and left on. It is then determined which of the one or more memory cells are to change state based on incoming user data that is to be written into the one or more memory cells. The one or more memory cells determined to change state and are still selected to be on are then written by applying a write-current pulse to the memory cells. In one exemplary embodiment, the one or more memory cells comprise one or more phase-change-type memory cell devices.
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公开(公告)号:US09589634B1
公开(公告)日:2017-03-07
申请号:US15087762
申请日:2016-03-31
Applicant: Intel Corporation
Inventor: Rakesh Jeyasingh , Nevil N. Gajera , Mase J Taub , Kiran Pangal
CPC classification number: G11C7/12 , G11C11/1657 , G11C11/1675 , G11C11/5678 , G11C13/0004 , G11C13/0028 , G11C13/0033 , G11C13/0069 , G11C2213/77
Abstract: Examples may include techniques to mitigate bias drift for memory cells of a memory device. A first memory cell coupled with a first word-line and a bit-line is selected for a write operation. A second memory cell coupled with a second word-line and the bit-line is de-selected for the write operation. First and second bias voltages are applied to the first word-line and the bit-line during the write operation to program the first memory cell. A third bias voltage is applied to the second word-line during the write operation to reduce or mitigate voltage bias to the second memory cell due to the second bias voltage applied to the bit-line to program the first memory cell.
Abstract translation: 示例可以包括减轻存储器件的存储器单元的偏移漂移的技术。 选择与第一字线和位线耦合的第一存储器单元用于写入操作。 与第二字线耦合的第二存储单元和位线被取消选择用于写入操作。 第一和第二偏置电压在写入操作期间被施加到第一字线和位线以对第一存储器单元进行编程。 在写入操作期间,第三偏置电压被施加到第二字线,以减少或减轻施加到位线的第二偏置电压来对第二存储器单元的电压偏置,以对第一存储器单元进行编程。
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公开(公告)号:US20160336048A1
公开(公告)日:2016-11-17
申请号:US15189314
申请日:2016-06-22
Applicant: Intel Corporation
Inventor: Mase J Taub , Sandeep K. Guliani , Kiran Pangal
CPC classification number: G11C13/0004 , G11C5/02 , G11C7/00 , G11C13/004 , G11C13/0069 , G11C2013/0076 , G11C2013/0078 , G11C2013/0092 , G11C2213/77
Abstract: A system and technique is disclosed for writing data in a cross-point memory. The state of one or more memory cells of the cross-point memory are sensed and then are continued to be selected and left on. It is then determined which of the one or more memory cells are to change state based on incoming user data that is to be written into the one or more memory cells. The one or more memory cells determined to change state and are still selected to be on are then written by applying a write-current pulse to the memory cells. In one exemplary embodiment, the one or more memory cells comprise one or more phase-change-type memory cell devices.
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公开(公告)号:US09384831B2
公开(公告)日:2016-07-05
申请号:US14289858
申请日:2014-05-29
Applicant: Intel Corporation
Inventor: Mase J Taub , Sandeep K. Guliani , Kiran Pangal
CPC classification number: G11C13/0004 , G11C5/02 , G11C7/00 , G11C13/004 , G11C13/0069 , G11C2013/0076 , G11C2013/0078 , G11C2013/0092 , G11C2213/77
Abstract: A system and technique is disclosed for writing data in a cross-point memory. The state of one or more memory cells of the cross-point memory are sensed and then are continued to be selected and left on. It is then determined which of the one or more memory cells are to change state based on incoming user data that is to be written into the one or more memory cells. The one or more memory cells determined to change state and are still selected to be on are then written by applying a write-current pulse to the memory cells. In one exemplary embodiment, the one or more memory cells comprise one or more phase-change-type memory cell devices.
Abstract translation: 公开了用于在交叉点存储器中写入数据的系统和技术。 检测交叉点存储器的一个或多个存储单元的状态,然后继续选择并保持。 然后,基于要写入一个或多个存储器单元的输入用户数据,确定一个或多个存储器单元中的哪一个将改变状态。 然后通过向存储器单元施加写入电流脉冲来写入确定为改变状态并且仍被选择为导通的一个或多个存储器单元。 在一个示例性实施例中,一个或多个存储器单元包括一个或多个相变型存储单元器件。
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