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    Techniques to mitigate bias drift for a memory device
    1.
    发明授权
    Techniques to mitigate bias drift for a memory device 有权
    减轻存储器件偏移漂移的技术

    公开(公告)号：US09589634B1

    公开(公告)日：2017-03-07

    申请号：US15087762

    申请日：2016-03-31

    Applicant: Intel Corporation

    Inventor： Rakesh Jeyasingh ,  Nevil N. Gajera ,  Mase J Taub ,  Kiran Pangal

    IPC: G11C13/00 ,  G11C11/56

    CPC classification number: G11C7/12 ,  G11C11/1657 ,  G11C11/1675 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/0033 ,  G11C13/0069 ,  G11C2213/77

    Abstract: Examples may include techniques to mitigate bias drift for memory cells of a memory device. A first memory cell coupled with a first word-line and a bit-line is selected for a write operation. A second memory cell coupled with a second word-line and the bit-line is de-selected for the write operation. First and second bias voltages are applied to the first word-line and the bit-line during the write operation to program the first memory cell. A third bias voltage is applied to the second word-line during the write operation to reduce or mitigate voltage bias to the second memory cell due to the second bias voltage applied to the bit-line to program the first memory cell.

    Abstract translation: 示例可以包括减轻存储器件的存储器单元的偏移漂移的技术。 选择与第一字线和位线耦合的第一存储器单元用于写入操作。 与第二字线耦合的第二存储单元和位线被取消选择用于写入操作。 第一和第二偏置电压在写入操作期间被施加到第一字线和位线以对第一存储器单元进行编程。 在写入操作期间，第三偏置电压被施加到第二字线，以减少或减轻施加到位线的第二偏置电压来对第二存储器单元的电压偏置，以对第一存储器单元进行编程。

    Techniques to mitigate bias drift for a memory device
    2.
    发明授权
    Techniques to mitigate bias drift for a memory device 有权

    公开(公告)号：US10026460B2

    公开(公告)日：2018-07-17

    申请号：US15415690

    申请日：2017-01-25

    Applicant: Intel Corporation

    Inventor： Rakesh Jeyasingh ,  Nevil N. Gajera ,  Mase J. Taub ,  Kiran Pangal

    IPC: G11C13/00 ,  G11C7/12 ,  G11C11/56

    Abstract: Examples may include techniques to mitigate bias drift for memory cells of a memory device. A first memory cell coupled with a first word-line and a bit-line is selected for a write operation. A second memory cell coupled with a second word-line and the bit-line is de-selected for the write operation. First and second bias voltages are applied to the first word-line and the bit-line during the write operation to program the first memory cell. A third bias voltage is applied to the second word-line during the write operation to reduce or mitigate voltage bias to the second memory cell due to the second bias voltage applied to the bit-line to program the first memory cell.

    Techniques to mitigate bias drift for a memory device
    3.
    发明授权
    Techniques to mitigate bias drift for a memory device 有权

    公开(公告)号：US10269396B2

    公开(公告)日：2019-04-23

    申请号：US16036756

    申请日：2018-07-16

    Applicant: Intel Corporation

    Inventor： Rakesh Jeyasingh ,  Nevil N Gajera ,  Mase J. Taub ,  Kiran Pangal

    IPC: G11C13/00 ,  G11C7/12 ,  G11C11/16 ,  G11C11/56

    Abstract: Examples may include techniques to mitigate bias drift for memory cells of a memory device. A first memory cell coupled with a first word-line and a bit-line is selected for a write operation. A second memory cell coupled with a second word-line and the bit-line is de-selected for the write operation. First and second bias voltages are applied to the first word-line and the bit-line during the write operation to program the first memory cell. A third bias voltage is applied to the second word-line during the write operation to reduce or mitigate voltage bias to the second memory cell due to the second bias voltage applied to the bit-line to program the first memory cell.

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