公开(公告)号：US20220158865A1

公开(公告)日：2022-05-19

申请号：US17665439

申请日：2022-02-04

Applicant: Intel Corporation

Inventor： Richard Marian THOMAIYAR ,  Janusz JURSKI ,  Myron LOEWEN ,  Zbigniew LUKWINSKI

IPC: H04L12/403 ,  H04L12/40 ,  H04L12/12

Abstract: Examples described herein relate to circuitry that is to manage communications to and from a manageability controller. In some examples, during communications on a first port, circuitry generates a bus busy condition for one or more other ports to block transactions from one or more devices.

公开(公告)号：US20220197859A1

公开(公告)日：2022-06-23

申请号：US17690950

申请日：2022-03-09

Applicant: Intel Corporation

Inventor： Janusz JURSKI ,  Myron LOEWEN ,  Mariusz ORIOL ,  Patrick SCHOELLER ,  Jerry BACKER ,  Richard Marian THOMAIYAR ,  Eliel LOUZOUN ,  Piotr MATUSZCZAK

IPC: G06F15/82 ,  G06F21/62

Abstract: Methods and apparatus for scalable MCTP infrastructure. A system is split into independent MCTP domains, wherein each MCTP domain uses Endpoint Identifiers (EIDs) for endpoint devices within the MCTP domain in a manner similar to conventional MCTP operations. A new class of MCTP devices (referred to as a Domain Controllers) is provided to enable inter-domain communication and communication with global devices. Global traffic originators or receivers like a BMC (Baseboard Management Controller), Infrastructure Processing Unit (IPU), Smart NIC (Network Interface Card), Debugger, or PROT (Platform Root or Trust) discover and establish two-way communication through the Domain Controllers to any of the devices in the target domain(s). The Domain Controllers are configured to implement tunneled connections between global devices and domain endpoint devices. The tunneled connections may employ encapsulated messages with outer and inner headers and/or augmented MCTP messages with repurposed fields used to store source and destination EIDs.

公开(公告)号：US20190042153A1

公开(公告)日：2019-02-07

申请号：US15857406

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Jawad B. KHAN ,  Sanjeev N. TRIKA ,  Myron LOEWEN ,  Peng LI

IPC: G06F3/06 ,  G06F12/10

Abstract: A mass storage device controller is described. The controller is to process first and second read requests received at an I/O interface of a mass storage device. The first read request includes a first logical block address. The first read request is to provide a first block stored within non volatile storage media of the mass storage device at the I/O interface. The first block is identified by the first logical block address. The second read request includes a second logical block address and specifies one or more bytes within a second block identified by the second block address and stored within the non volatile storage media. The second read request is to provide the one or more bytes at the I/O interface.

公开(公告)号：US20220171669A1

公开(公告)日：2022-06-02

申请号：US17671903

申请日：2022-02-15

Applicant: Intel Corporation

Inventor： Rajesh BHASKAR ,  George VERGIS ,  Myron LOEWEN ,  Matthew A. SCHNOOR

IPC: G06F11/07 ,  G06F11/14 ,  G06F13/42 ,  G06F13/16

Abstract: An apparatus and method to monitor status of a serial data signal on a low speed serial bus is provided. A controller configures a watchdog timer in each target device, sends a heart-beat command to all of the target devices over the low speed serial bus prior to the expiration of the watchdog timer and issues a broadcast read command to any one of the target devices on the low speed serial bus. A response to the broadcast read command confirms that the low speed serial bus is functional. If a response is not received, the low speed serial bus is not functional and the controller initiates a broadcast reset command to initialize all target devices on the low speed serial bus.

公开(公告)号：US20190042152A1

公开(公告)日：2019-02-07

申请号：US15833955

申请日：2017-12-06

Applicant: Intel Corporation

Inventor： Sanjeev N. TRIKA ,  Peng LI ,  Jawad B. KHAN ,  Myron LOEWEN

IPC: G06F3/06 ,  G06F11/07 ,  H04L29/08

Abstract: Examples include techniques for implementing a write transaction to two or more memory devices in a storage device. In some examples, the write transaction includes an atomic write transaction from an application or operating system executing on a computing platform to a storage device coupled with the computing platform. For these examples, the storage device includes a storage controller to receive an atomic multimedia write transaction request to write first data and second data; cause the first data to be stored in a first memory device, and cause the second data to be stored in a second memory device, simultaneously and atomically.