公开(公告)号：US09224465B2

公开(公告)日：2015-12-29

申请号：US14221572

申请日：2014-03-21

Applicant: Intel Corporation

Inventor： Nathan R. Franklin ,  Sandeep K. Guliani ,  Mase J. Taub ,  Kiran Pangal

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/004 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0033 ,  G11C2213/76

Abstract: The present disclosure relates to a cross-point memory bias scheme. An apparatus includes a memory controller including a word line (WL) control module and a bit line (BL) control module, the memory controller configured to initiate selection of a target memory cell; a sense module configured to determine whether the target memory cell has been selected; and a C-cell bias module configured to establish a C-cell bias if the target cell is not selected.

Abstract translation: 本公开涉及一种交叉点存储器偏置方案。 一种装置，包括：存储器控制器，包括字线（WL）控制模块和位线控制模块，所述存储器控制器被配置为启动目标存储器单元的选择; 感测模块​​，其被配置为确定所述目标存储器单元是否已被选择; 以及配置为如果所述目标单元未被选择则建立C单元偏压的C单元偏置模块。

公开(公告)号：US09286975B2

公开(公告)日：2016-03-15

申请号：US14204376

申请日：2014-03-11

Applicant: Intel Corporation

Inventor： Daniel J. Chu ,  Kiran Pangal ,  Nathan R. Franklin ,  Prashant S. Damle ,  Hu Chaohong

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/56

CPC classification number: G11C13/004 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0033 ,  G11C13/0035 ,  G11C13/0061 ,  G11C2013/0047 ,  G11C2013/0052

Abstract: The present disclosure relates to mitigating read disturb in a cross-point memory. An apparatus may include a memory controller configured to select a target memory cell for a memory access operation. The memory controller includes a sense module configured to determine whether a snap back event occurs during a sensing interval; and a write back module configured to write back a logic one to the memory cell if a snap back event is detected.

Abstract translation: 本公开涉及减轻交叉点存储器中的读取干扰。 设备可以包括被配置为选择用于存储器访问操作的目标存储器单元的存储器控​​制器。 存储器控制器包括感测模块，其被配置为确定在感测间隔期间是否发生快照事件; 以及写回模块，被配置为如果检测到快照事件，则将逻辑1写回到所述存储器单元。

公开(公告)号：US09502108B2

公开(公告)日：2016-11-22

申请号：US14863827

申请日：2015-09-24

Applicant: Intel Corporation

Inventor： Nathan R. Franklin ,  Kiran Pangal

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/24 ,  G11C11/56

CPC classification number: G11C13/0069 ,  G11C11/24 ,  G11C11/5642 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0045 ,  G11C2013/0076 ,  G11C2013/0078 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2207/063

Abstract: Described herein are techniques related to one or more systems, apparatuses, methods, etc. for programming a memory cell through the use of a program pulse.

公开(公告)号：US20160012892A1

公开(公告)日：2016-01-14

申请号：US14863827

申请日：2015-09-24

Applicant: Intel Corporation

Inventor： Nathan R. Franklin ,  Kiran Pangal

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C11/24 ,  G11C11/5642 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0045 ,  G11C2013/0076 ,  G11C2013/0078 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2207/063

Abstract: Described herein are techniques related to one or more systems, apparatuses, methods, etc. for programming a memory cell through the use of a program pulse.