公开(公告)号：US20240113118A1

公开(公告)日：2024-04-04

申请号：US17956188

申请日：2022-09-29

Applicant: Intel Corporation

Inventor： Tao Chu ,  Minwoo Jang ,  Yanbin Luo ,  Paul A. Packan

IPC: H01L27/092

CPC classification number: H01L27/0922 ,  H01L27/0924

Abstract: Integrated circuit dies, apparatuses, systems, and techniques, are described herein related to low and ultra-low threshold voltage transistor cells. A first transistor cell includes separate semiconductor bodies contacted by separate gate electrodes having a dielectric material therebetween. A second transistor cell includes separate semiconductor bodies contacted by a shared gate electrode that couples to both semiconductor bodies. Transistors of the second transistor cell may be operated at a lower threshold voltage than those of the first transistor cell due to increased strain on the semiconductor bodies from the shared gate electrode.

公开(公告)号：US11664452B2

公开(公告)日：2023-05-30

申请号：US17085981

申请日：2020-10-30

Applicant: Intel Corporation

Inventor： Pratik A. Patel ,  Mark Y. Liu ,  Jami A. Wiedemer ,  Paul A. Packan

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/225 ,  H01L21/324 ,  H01L29/08 ,  H01L29/24 ,  H01L29/267

CPC classification number: H01L29/7848 ,  H01L21/2253 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/24 ,  H01L29/267 ,  H01L29/66492 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  H01L29/7851

Abstract: A method including forming an opening in a junction region of a fin on and extending from a substrate; introducing a doped semiconductor material in the opening; and thermal processing the doped semiconductor material. A method including forming a gate electrode on a fin extending from a substrate; forming openings in the fin adjacent opposite sides of the gate electrode; introducing a doped semiconductor material in the openings; and thermally processing the doped semiconductor material sufficient to induce the diffusion of a dopant in the doped semiconductor material. An apparatus including a gate electrode transversing a fin extending from a substrate; and semiconductor material filled openings in junction regions of the fin adjacent opposite sides of the gate electrode, wherein the semiconductor material comprises a dopant.

公开(公告)号：US10304956B2

公开(公告)日：2019-05-28

申请号：US15038969

申请日：2013-12-27

Applicant: INTEL CORPORATION ,  Pratik A. Patel ,  Mark Y. Liu ,  Jami A. Wiedemer ,  Paul A. Packan

Inventor： Pratik A. Patel ,  Mark Y. Liu ,  Jami A. Wiedemer ,  Paul A. Packan

IPC: H01L29/08 ,  H01L29/24 ,  H01L29/66 ,  H01L29/78 ,  H01L21/225 ,  H01L21/324 ,  H01L29/267

Abstract: A method including forming an opening in a junction region of a fin on and extending from a substrate; introducing a doped semiconductor material in the opening; and thermal processing the doped semiconductor material. A method including forming a gate electrode on a fin extending from a substrate; forming openings in the fin adjacent opposite sides of the gate electrode; introducing a doped semiconductor material in the openings; and thermally processing the doped semiconductor material sufficient to induce the diffusion of a dopant in the doped semiconductor material. An apparatus including a gate electrode transversing a fin extending from a substrate; and semiconductor material filled openings in junction regions of the fin adjacent opposite sides of the gate electrode, wherein the semiconductor material comprises a dopant.