公开(公告)号：US20160378551A1

公开(公告)日：2016-12-29

申请号：US14748515

申请日：2015-06-24

Applicant: Intel Corporation

Inventor： Priya N. Vaidya ,  Premanand Sakarda

IPC: G06F9/48

CPC classification number: G06F9/4893 ,  G06F1/329 ,  G06F9/5094

Abstract: Systems and methods may provide for making a power efficiency determination at runtime based on one or more runtime usage notifications and scheduling a workload for execution on a hardware accelerator if the power efficiency determination indicates that execution of the workload on the hardware accelerator will be more efficient than execution of the workload on a host processor. Additionally, the workload may be scheduled for execution on the host processor if the power efficiency determination indicates that execution of the workload on the host processor will be more efficient than execution of the workload on the hardware accelerator. In one example, making the power efficiency determination includes applying one or more configurable rules to at least one of the one or more runtime usage notifications.

Abstract translation: 系统和方法可以提供在运行时基于一个或多个运行时使用通知进行功率效率确定，并且如果功率效率确定指示硬件加速器上的工作负载的执行将更有效，则调度用于在硬件加速器上执行的工作负载 而不是在主机处理器上执行工作负载。 另外，如果功率效率确定指示主机处理器上的工作负载的执行将比在硬件加速器上的工作负载的执行更有效，那么工作负载可以被安排在主机处理器上执行。 在一个示例中，进行功率效率确定包括将一个或多个可配置规则应用于所述一个或多个运行时使用通知中的至少一个。

公开(公告)号：US09766672B2

公开(公告)日：2017-09-19

申请号：US13847036

申请日：2013-03-19

Applicant: Intel Corporation

Inventor： Bryan C. Morgan ,  Priya N. Vaidya ,  Premanand Sakarda ,  Marlon A. Moncrieffe

IPC: G06F1/00 ,  G06F1/26 ,  G06F1/32

CPC classification number: G06F1/26 ,  G06F1/3203 ,  G06F1/3246 ,  G06F1/3275 ,  Y02D10/13 ,  Y02D10/14

Abstract: In one embodiment, an electronic apparatus comprises at least one processor and a computer readable medium coupled to the processor and comprising logic instructions encoded in the computer readable medium, wherein the instructions, when executed in a processing system, cause the processing system to perform operations comprising initializing a direct memory access profiler in an electronic system, wherein the direct memory access is coupled to a policy manager in the electronic system, measuring at least one memory consumption characteristic of the electronic system, communicating the at least one memory consumption characteristic to a policy manager of the electronic system, and using the at least one memory consumption characteristic to adjust a power state of the electronic system.

公开(公告)号：US12141015B2

公开(公告)日：2024-11-12

申请号：US17127899

申请日：2020-12-18

Applicant: Intel Corporation

Inventor： Deepak S Kirubakaran ,  Ramakrishnan Sivakumar ,  Russell Fenger ,  Monica Gupta ,  Jianwei Dai ,  Premanand Sakarda ,  Guy Therien ,  Rajshree Chabukswar ,  Chad Gutierrez ,  Renji Thomas

IPC: G06F1/3287 ,  G06F1/3228

Abstract: A hardware and software coordinated processor power state policy (e.g., policy for C-state) that delivers optimal power state selection by taking in to account the performance and/or responsiveness needs of thread expected to be scheduled on the core entering idle, to achieve improved IPC and performance for cores running user critical tasks. The scheme provides the ability to deliver responsiveness gains for important and/or user-critical threads running on a system-on-chip. A power management controller coupled to the plurality of processing cores, wherein the power management controller receives a hint from an operating system indicative of a bias towards a power state or performance state for at least one of the processing cores of the plurality of processing cores based on a priority of a thread in context switch.

公开(公告)号：US20210349519A1

公开(公告)日：2021-11-11

申请号：US16870514

申请日：2020-05-08

Applicant: Intel Corporation

Inventor： Leo Aqrabawi ,  Chia-hung S. Kuo ,  James G. Hermerding II ,  Premanand Sakarda ,  Bijan Arbab ,  Kelan Silvester

IPC: G06F1/3234 ,  G06F12/0815 ,  G06N20/00 ,  G06N5/04

Abstract: A machine-learning (ML) scheme running a software driver stack to learn user habits of entry into low power states, such as Modern Connect Standby (ModCS), and duration depending on time of day, and/or system telemetry. The ML creates a High Water Mark (HWM) number of dirty cache lines (DL) as a hint to a power agent. A power agent algorithm uses these hints and actual system's number of DL to inform the low power state entry decision (such as S0i4 vs. S0i3 entry decision) for a computing system.

公开(公告)号：US20230161613A1

公开(公告)日：2023-05-25

申请号：US17535458

申请日：2021-11-24

Applicant: Intel Corporation

Inventor： Jaishankar Rajendran ,  Jun Nakajima ,  Prashant Kodali ,  Karthik Varadarajan ,  Premanand Sakarda ,  Zhiyuan Lv ,  Vaibhav Shankar

IPC: G06F9/455

CPC classification number: G06F9/45558 ,  G06F9/45545

Abstract: Techniques and mechanisms for a host passthrough to be performed based on the execution of a hardware identification instruction with a virtual machine (VM). In an embodiment, a hypervisor process sets a value of a control parameter corresponding to a resource of the VM. The control parameter indicates whether the VM resource is authorized to avail of a host passthrough functionality of a processor which executes the hypervisor process. The control parameter is evaluated, based on a central processing unit identification (CPUID) instruction of a guest operating system which is executed with the VM, to determine whether the CPUID instruction is to result in a host passthrough or a VM exit. In another embodiment, a shared memory resource is searched to determine whether execution of the CPUID instruction is to retrieve information without the use of either the host passthrough or the VM exit.

公开(公告)号：US11500444B2

公开(公告)日：2022-11-15

申请号：US16870514

申请日：2020-05-08

Applicant: Intel Corporation

Inventor： Leo Aqrabawi ,  Chia-hung S. Kuo ,  James G. Hermerding, II ,  Premanand Sakarda ,  Bijan Arbab ,  Kelan Silvester

IPC: G06F1/00 ,  G06F1/3234 ,  G06F12/0815 ,  G06N5/04 ,  G06N20/00 ,  G06F1/3203

Abstract: A machine-learning (ML) scheme running a software driver stack to learn user habits of entry into low power states, such as Modern Connect Standby (ModCS), and duration depending on time of day, and/or system telemetry. The ML creates a High Water Mark (HWM) number of dirty cache lines (DL) as a hint to a power agent. A power agent algorithm uses these hints and actual system's number of DL to inform the low power state entry decision (such as S0i4 vs. S0i3 entry decision) for a computing system.

公开(公告)号：US20220197367A1

公开(公告)日：2022-06-23

申请号：US17127899

申请日：2020-12-18

Applicant: Intel Corporation

Inventor： Deepak S Kirubakaran ,  Ramakrishnan Sivakumar ,  Russell Fenger ,  Monica Gupta ,  Jianwei Dai ,  Premanand Sakarda ,  Guy Therien ,  Rajshree Chabukswar ,  Chad Gutierrez ,  Renji Thomas

IPC: G06F1/3287 ,  G06F1/3228

Abstract: A hardware and software coordinated processor power state policy (e.g., policy for C-state) that delivers optimal power state selection by taking in to account the performance and/or responsiveness needs of thread expected to be scheduled on the core entering idle, to achieve improved IPC and performance for cores running user critical tasks. The scheme provides the ability to deliver responsiveness gains for important and/or user-critical threads running on a system-on-chip. A power management controller coupled to the plurality of processing cores, wherein the power management controller receives a hint from an operating system indicative of a bias towards a power state or performance state for at least one of the processing cores of the plurality of processing cores based on a priority of a thread in context switch.

公开(公告)号：US09619284B2

公开(公告)日：2017-04-11

申请号：US13645081

申请日：2012-10-04

Applicant: Intel Corporation

Inventor： Premanand Sakarda

IPC: G06F9/48 ,  G06F9/38 ,  G06F1/32

CPC classification number: G06F9/4893 ,  G06F1/329 ,  G06F9/3885 ,  G06F2209/5019 ,  Y02D10/24

Abstract: In one embodiment, a policy manager may receive operating system scheduling information, performance prediction information for at least one future quantum, and current processor utilization information, and determine a performance prediction for a future quantum and whether to cause a switch between asymmetric cores of a multicore processor based at least in part on this received information. Other embodiments are described and claimed.