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公开(公告)号：US11573722B2
公开(公告)日：2023-02-07
申请号：US16987057
申请日：2020-08-06
Applicant: Intel Corporation
Inventor： Rasika Subramanian , Lidia Warnes , Francesc Guim Bernat , Mark A. Schmisseur , Durgesh Srivastava
IPC: G06F3/06
Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to provide an interface to a pooled memory that is configured as a combination of local memory and remote memory, wherein the remote memory is shared between multiple compute nodes, allocate respective memory portions of the pooled memory to respective tenants, associate respective memory balloons with the respective tenants that correspond to the allocated respective memory portions, and manage the respective memory balloons based on the respective tenants and two or more memory tiers associated with the pooled memory. Other embodiments are disclosed and claimed.
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公开(公告)号：US20230333738A1
公开(公告)日：2023-10-19
申请号：US18142942
申请日：2023-05-03
Applicant: Intel Corporation
Inventor： Rasika Subramanian , Lidia Warnes , Francesc Guim Bernat , Mark A. Schmisseur , Durgesh Srivastava
IPC: G06F3/06
CPC classification number: G06F3/0608 , G06F3/0631 , G06F3/0665 , G06F3/0673
Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to allocate a first memory portion to a first application as a combination of a local memory and remote memory, wherein the remote memory is shared between multiple compute nodes, and manage a first memory balloon associated with the first memory portion based on two or more memory tiers associated with the local memory and the remote memory. Other embodiments are disclosed and claimed.
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公开(公告)号：US11681439B2
公开(公告)日：2023-06-20
申请号：US16914124
申请日：2020-06-26
Applicant: Intel Corporation
Inventor： Rasika Subramanian , Lidia Warnes , Francesc Guim Bernat , Mark A. Schmisseur , Durgesh Srivastava
IPC: G06F3/06
CPC classification number: G06F3/0608 , G06F3/0631 , G06F3/0665 , G06F3/0673
Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to allocate a first memory portion to a first application as a combination of a local memory and remote memory, wherein the remote memory is shared between multiple compute nodes, and manage a first memory balloon associated with the first memory portion based on two or more memory tiers associated with the local memory and the remote memory. Other embodiments are disclosed and claimed.
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公开(公告)号：US20190094926A1
公开(公告)日：2019-03-28
申请号：US15718451
申请日：2017-09-28
Applicant: Intel Corporation
Inventor： Rasika Subramanian , Francesc Guim Bernat , Steen Larsen
CPC classification number: G06F1/3206 , G06F1/3209 , G06F1/3287
Abstract: A computing device, a method and a system to control power. The computing device is configured to be used as part of a network fabric including a plurality of nodes and a plurality of pooled accelerators coupled to the nodes. The computing device includes: a memory storing instructions; and processing circuitry configured to perform the instructions. The processing circuitry is to receive respective requests from respective ones of the plurality of nodes, the requests addressed to a plurality of corresponding accelerators, each of the respective requests including information on a kernel to be executed by a corresponding accelerator, on the corresponding accelerator, and on a performance target for execution of the kernel. The processing circuitry is further to, based on the information in said each of the respective requests, control a power supply to the corresponding accelerator.
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Patent Agency Ranking
公开(公告)号：US12210434B2
公开(公告)日：2025-01-28
申请号：US16914305
申请日：2020-06-27
Applicant: Intel Corporation
Inventor： Bin Li , Ren Wang , Kshitij Arun Doshi , Francesc Guim Bernat , Yipeng Wang , Ravishankar Iyer , Andrew Herdrich , Tsung-Yuan Tai , Zhu Zhou , Rasika Subramanian
Abstract: An apparatus and method for closed loop dynamic resource allocation. For example, one embodiment of a method comprises: collecting data related to usage of a plurality of resources by a plurality of workloads over one or more time periods, the workloads including priority workloads associated with one or more guaranteed performance levels and best effort workloads not associated with guaranteed performance levels; analyzing the data to identify resource reallocations from one or more of the priority workloads to one or more of the best effort workloads in one or more subsequent time periods while still maintaining the guaranteed performance levels; reallocating the resources from the priority workloads to the best effort workloads for the subsequent time periods; monitoring execution of the priority workloads with respect to the guaranteed performance level during the subsequent time periods; and preemptively reallocating resources from the best effort workloads to the priority workloads during the subsequent time periods to ensure compliance with the guaranteed performance level and responsive to detecting that the guaranteed performance level is in danger of being breached.
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公开(公告)号：US11983408B2
公开(公告)日：2024-05-14
申请号：US18142942
申请日：2023-05-03
Applicant: Intel Corporation
Inventor： Rasika Subramanian , Lidia Warnes , Francesc Guim Bernat , Mark A. Schmisseur , Durgesh Srivastava
IPC: G06F3/06
CPC classification number: G06F3/0608 , G06F3/0631 , G06F3/0665 , G06F3/0673
Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to allocate a first memory portion to a first application as a combination of a local memory and remote memory, wherein the remote memory is shared between multiple compute nodes, and manage a first memory balloon associated with the first memory portion based on two or more memory tiers associated with the local memory and the remote memory. Other embodiments are disclosed and claimed.
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公开(公告)号：US11507430B2
公开(公告)日：2022-11-22
申请号：US16144962
申请日：2018-09-27
Applicant: Intel Corporation
Inventor： Rasika Subramanian , Francesc Guim Bernat , David Zimmerman
Abstract: Examples described herein can be used to determine and suggest a computing resource allocation for a workload request made from an edge gateway. The computing resource allocation can be suggested using computing resources provided by an edge server cluster. Telemetry data and performance indicators of the workload request can be tracked and used to determine the computing resource allocation. Artificial intelligence (AI) and machine learning (ML) techniques can be used in connection with a neural network to accelerate determinations of suggested computing resource allocations based on hundreds to thousands (or more) of telemetry data in order to suggest a computing resource allocation. Suggestions made can be accepted or rejected by a resource allocation manager for the edge gateway and the edge server cluster.
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公开(公告)号：US20200326861A1
公开(公告)日：2020-10-15
申请号：US16914124
申请日：2020-06-26
Applicant: Intel Corporation
Inventor： Rasika Subramanian , Lidia Warnes , Francesc Guim Bernat , Mark A. Schmisseur , Durgesh Srivastava
IPC: G06F3/06
Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to allocate a first memory portion to a first application as a combination of a local memory and remote memory, wherein the remote memory is shared between multiple compute nodes, and manage a first memory balloon associated with the first memory portion based on two or more memory tiers associated with the local memory and the remote memory. Other embodiments are disclosed and claimed.
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公开(公告)号：US10444813B2
公开(公告)日：2019-10-15
申请号：US15718451
申请日：2017-09-28
Applicant: Intel Corporation
Inventor： Rasika Subramanian , Francesc Guim Bernat , Steen Larsen
IPC: G06F1/32 , G06F1/3206 , G06F1/3287 , G06F1/3209
Abstract: A computing device, a method and a system to control power. The computing device is configured to be used as part of a network fabric including a plurality of nodes and a plurality of pooled accelerators coupled to the nodes. The computing device includes: a memory storing instructions; and processing circuitry configured to perform the instructions. The processing circuitry is to receive respective requests from respective ones of the plurality of nodes, the requests addressed to a plurality of corresponding accelerators, each of the respective requests including information on a kernel to be executed by a corresponding accelerator, on the corresponding accelerator, and on a performance target for execution of the kernel. The processing circuitry is further to, based on the information in said each of the respective requests, control a power supply to the corresponding accelerator.
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