公开(公告)号：US20240061942A1

公开(公告)日：2024-02-22

申请号：US18496315

申请日：2023-10-27

Applicant: Intel Corporation

Inventor： Reuven Elbaum ,  Gyora Benedek ,  Avinash L. Varna ,  David Novick

IPC: G06F21/60 ,  H04L9/32

CPC classification number: G06F21/602 ,  H04L9/3236

Abstract: An apparatus is described including cryptography circuitry to generate authentication tags to provide integrity protection for plaintext and ciphertext.

公开(公告)号：US20220029838A1

公开(公告)日：2022-01-27

申请号：US17481771

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Uri Bear ,  Reuven Elbaum ,  Elad Peer

IPC: H04L9/32

Abstract: The disclosure generally provides methods, systems and apparatus to construct a Physically Unclonable Function (PUF) value for an electronic package based on the package's internal components and their interconnects. In one embodiment, the package is a System-On-Chip (SOC) having a plurality of dielets and a plurality of interconnect connecting the dielets. Each of the dielets and each of the interconnects (at one or more locations) may define an entropy source. each entropy source may have an entropy value. Each entropy source communicates an initial entropy value to a PUF aggregator. The PUF aggregator receives and/or aggregates the various entropies from the various entropy sources to construct the native SOC PUF value. The native SOC PUF value defines the authentic PUF value of the SOC at SOC release. Any deviation from the native SOC PUF value may be deemed a security breach of the SOC.

公开(公告)号：US11984512B2

公开(公告)日：2024-05-14

申请号：US17033444

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Uri Bear ,  Elad Peer ,  Elena Sidorov ,  Rami Sudai ,  Reuven Elbaum ,  Steve J. Brown

IPC: H01L29/788 ,  G11C16/04 ,  H01L29/423 ,  H01L29/66 ,  H10B41/00 ,  H10B43/00

CPC classification number: H01L29/788 ,  G11C16/0408 ,  H01L29/42324 ,  H01L29/66825 ,  H10B41/00 ,  H10B43/00

Abstract: In one embodiment, memory cell includes a control gate, a floating gate, a substrate comprising a source region and a drain region, a first isolator between the control gate and floating gate, and a second isolator between the floating gate and the substrate. The memory cell is configured to have a retention time that is within a statistical window around a selected lifespan. The selected lifespan may be less than ten years, such as, for example, less than one year, less than one month, or less than one week.

公开(公告)号：US11645185B2

公开(公告)日：2023-05-09

申请号：US17033272

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Reuven Elbaum ,  Chaim Shen-Orr ,  Assaf Admoni

IPC: G06F11/00 ,  G06F11/34 ,  G06F11/07 ,  G06F9/48 ,  G06F9/38 ,  G06F11/32

CPC classification number: G06F11/3409 ,  G06F9/3836 ,  G06F9/4868 ,  G06F11/0772 ,  G06F11/327

Abstract: Micro-architectural fault detectors are described. An example of storage mediums includes instructions for receiving one or more micro instructions for scheduling in a processor, the processor including one or more processing resources; and performing fault detection in performance of the one or more micro instructions utilizing one or more of a first idle canary detection mode, wherein the first mode includes assigning at least one component as an idle canary detector to perform a canary process with an expected outcome, and a second micro-architectural redundancy execution mode, wherein the second mode includes replicating a first micro instruction to generate micro instructions for performance by a set of processing resources.

公开(公告)号：US20210374256A1

公开(公告)日：2021-12-02

申请号：US17401459

申请日：2021-08-13

Applicant: Intel Corporation

Inventor： Reuven Elbaum ,  Gyora Benedek ,  Avinash L. Varna ,  David Novick

IPC: G06F21/60 ,  H04L9/32

Abstract: An apparatus is described including cryptography circuitry to generate authentication tags to provide integrity protection for plaintext and ciphertext.

公开(公告)号：US20220100629A1

公开(公告)日：2022-03-31

申请号：US17033272

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Reuven Elbaum ,  Chaim Shen-Orr ,  Assaf Admoni

IPC: G06F11/34 ,  G06F11/07 ,  G06F11/32 ,  G06F9/38 ,  G06F9/48

Abstract: Micro-architectural fault detectors are described. An example of storage mediums includes instructions for receiving one or more micro instructions for scheduling in a processor, the processor including one or more processing resources; and performing fault detection in performance of the one or more micro instructions utilizing one or more of a first idle canary detection mode, wherein the first mode includes assigning at least one component as an idle canary detector to perform a canary process with an expected outcome, and a second micro-architectural redundancy execution mode, wherein the second mode includes replicating a first micro instruction to generate micro instructions for performance by a set of processing resources.

公开(公告)号：US20220083651A1

公开(公告)日：2022-03-17

申请号：US17024107

申请日：2020-09-17

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Avinash L. Varna ,  Reuven Elbaum ,  Manoj Sastry

IPC: G06F21/55

Abstract: Protection of authentication tag computation against power and electromagnetic side-channel attacks is described. An example of one or more storage mediums includes instructions for performing a process for calculation of an authentication tag for a data encryption operation, including generating one or more random values; receiving multiple data blocks for calculation, and performing calculation utilizing the received data blocks and the one or more random values to generate intermediate values; performing a data accumulation operation to accumulate random values in calculation of the data blocks; and calculating the authentication tag based at least in part on the generated intermediate values and the accumulated random values.

公开(公告)号：US20190004972A1

公开(公告)日：2019-01-03

申请号：US15637524

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Uri Bear ,  Gyora Benedek ,  Baruch Chaikin ,  Jacob Jack Doweck ,  Reuven Elbaum ,  Dimitry Kloper ,  Elad Peer ,  Chaim Shen-orr ,  Yonatan Shlomovich

IPC: G06F12/14 ,  G06F12/1009

Abstract: Various systems and methods for detecting and preventing side-channel attacks, including attacks aimed at discovering the location of KASLR-randomized privileged code sections in virtual memory address space, are described. In an example, a computing system includes electronic operations for detecting unauthorized attempts to access kernel virtual memory pages via trap entry detection, with operations including: generating a trap page with a physical memory address; assigning a phantom page at an open location in the privileged portion of the virtual memory address space; generating a plurality of phantom page table entries corresponding to an otherwise-unmapped privileged virtual memory region; placing the trap page in physical memory and placing the phantom page table entry in a page table map; and detecting an access to the trap page via the phantom page table entry, to trigger a response to a potential attack.

公开(公告)号：US11816229B2

公开(公告)日：2023-11-14

申请号：US17401459

申请日：2021-08-13

Applicant: Intel Corporation

Inventor： Reuven Elbaum ,  Gyora Benedek ,  Avinash L. Varna ,  David Novick

IPC: G06F21/00 ,  G06F21/60 ,  H04L9/32

CPC classification number: G06F21/602 ,  H04L9/3236

Abstract: An apparatus is described including cryptography circuitry to generate authentication tags to provide integrity protection for plaintext and ciphertext.

公开(公告)号：US20230185905A1

公开(公告)日：2023-06-15

申请号：US18066913

申请日：2022-12-15

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Avinash L. Varna ,  Reuven Elbaum ,  Manoj Sastry

IPC: G06F21/55

CPC classification number: G06F21/55 ,  G06F2221/034

Abstract: Protection of authentication tag computation against power and electromagnetic side-channel attacks is described. An example of one or more storage mediums includes instructions for performing a process for calculation of an authentication tag for a data encryption operation, including generating one or more random values; receiving multiple data blocks for calculation, and performing calculation utilizing the received data blocks and the one or more random values to generate intermediate values; performing a data accumulation operation to accumulate random values in calculation of the data blocks; and calculating the authentication tag based at least in part on the generated intermediate values and the accumulated random values.